VEGA Microprocessors
VEGA Microprocessor logo
VEGA Processor logo
General information
Designed byCentre for Development of Advanced Computing
Common manufacturer(s)
Architecture and classification
ApplicationIoT, Storage, Smart NICs, Edge Analytics, Data Analytics, Autonomous Machines, Storage, Networking
Instruction setRISC-V
Variant(s)
  • VEGA ET1031
  • VEGA AS1061
  • VEGA AS1161
  • VEGA AS2161
  • VEGA AS4161

VEGA Microprocessors (also referred to as VEGA processors) is an initiative to develop a portfolio of processors, and their hardware ecosystem, by the Centre for Development of Advanced Computing (C-DAC) in India.[1][2] The portfolio includes several indigenously-developed processors based on the RISC-V instruction set architecture (ISA).[3][4][5]

The Microprocessor Development Programme (MDP) was initiated and funded by MeitY with the mission objective to design and develop indigenously, a family of Microprocessors, related IPs and the complete ecosystem to enable fully indigenous product development that meets various requirements in the strategic, industrial and commercial sectors. As part of the project C-DAC has successfully developed the VEGA series of microprocessors [6] in soft IP form, which include32-bit Single-core (In-order), 64-bit Single-core (In-order & Out-of-order), 64-bit Dual-core (Out-of-order), and 64-bit Quad-core (Out-of-order).

THEJAS32 Chip Image
THEJAS32 SoC ASIC from VEGA Processors

Vega processors are used in “Swadeshi Microprocessor Challenge- Innovate Solutions for #Atmanirbhar Bharat”.[7][8][9][10]

Products

The initiative has developed the following product lines:[5]

ARIES

The ARIES microcontroller boards have been described by researchers as alternatives to Arduino Uno boards.[5][11]

Processor variants

There are many variants for VEGA microprocessors,[12] including:

VEGA ET1031

VEGA ET1031 is a compact and efficient 32-bit, 3-stage in-order processor based on RISC-V instruction set architecture. This microprocessor can be used as an effective work horse in low power IoT applications. It is based on RISC-V (RV32IM) Instruction Set Architecture and contains a high-performance multiply/divide unit, configurable AXI4 or AHB external interface, optional MPU (Memory Protection Unit), Platform Level Interrupt Controller and advanced Integrated Debug Controller.

VEGA AS1061

VEGA AS1061 is a 64-bit, 6 stage in-order pipelined processor based on RISC-V 64GC (RV64IMAFDC) Instruction Set Architecture. Its usage mainly aimed at low power embedded applications. The core has a highly optimized 6-stage in-order pipeline with supervisor support and has the capability to boot Linux or other Operating systems. The pipeline is highly configurable and can support the RISC-V RV64 IMAFDC extensions. The AXI or AHB standard interface provided enables ease of system integration and a JTAG interface is provided for debug support. It also supports a highly optimized branch predictor with BTB, BHT and RAS along with Optional Memory Management Unit (MMU), Configurable, L1 caches, Platform Level Interrupt Controller etc.

VEGA AS1161

VEGA AS1161 features an out-of-order processing engine with a 16-stage pipeline enabling it to meet next gen computational requirements. The design supports RISC-V 64G (RV64IMAFD) Instruction Set Architecture in a 13-16 stage out-of-order pipeline implementation. The processor supports single and double precision floating point instructions, and a fully featured memory with Memory Management Unit and Page-based virtual memory for Linux-based applications. AS1161 is optimized for high performance, integrating an Advanced branch predictor for efficient branch execution, Instruction and Data caches. Features also include PLIC and vectored interrupts for serving various types of system events. An AXI4- / ACE, AHB- compliant external interface facilitates ease of system integration. There is also a WFI mode for power management, and JTAG debug interface for development support.

VEGA AS2161

VEGA AS2161 features a dual core out-of-order processing engine with a 16-stage pipeline for high performance compute requirements. The design supports RISC-V 64G (RV64IMAFD) Instruction Set Architecture in a 13-16 stage out-of-order pipeline implementation. The processor also supports single and double precision floating point instructions, and MMU for Linux-based applications. This high-performance application core comes with advanced branch prediction for efficient branch execution, Instruction and Data caches. This is ideal for applications requiring high-throughput performance e.g., Media server, Single Board Computer, Storage, Networking etc. A Cache coherent interconnect along with a highly optimized L2 cache is also part of the design.

VEGA AS4161

VEGA AS4161 features a quad core out-of-order processing engine with a 16-stage pipeline for high performance compute requirements. The design supports RISC-V 64G (RV64IMAFD) Instruction Set Architecture in a 13-16 stage out-of-order pipeline implementation along with advanced branch prediction unit, L1 Caches, MMU, TLB etc. This is ideal for applications requiring high-throughput performance e.g., Storage, Networking, etc. An AXI4- / ACE, AHB- compliant external interface is used to connect multiple cores to the interconnect and memory subsystem. A Cache coherent interconnect along with a highly optimized L2 cache is a part of the design.

SoCs

THEJAS32

THEJAS32 SoC [13] is built around VEGA ET1031, a 32-bit high performance microcontroller class processor consisting of a 3-stage in-order RISC-V based core. The peripherals available in THEJAS32 SoC are GPIO, Interrupt Controller, Timers, RAM, SPI, UART, I2C, PWM and ADC. This is targeted for applications like sensor fusion, smart meters, small IoT devices, wearable devices, electronic toys, etc. This SoC is ported on to Digilent Artix-7 35T FPGA development board, extensively used by the Swadeshi Microprocessor Challenge Participants. Also THEAJS32 SoC ASIC fabricated in SilTerra 130 nm technology.

THEJAS64

THEJAS64 SoC [13] is built around VEGA AS1061, a 64-bit processor with a 6-stage in-order pipeline optimized for high performance. This processor consists of an efficient branch predictor and instruction and data caches and is targeted for applications like IoT devices, motor control, wearable devices, high-performance embedded, consumer electronics and industrial automation. The peripherals available in this SoC are GPIO, Interrupt Controller, Timers, DDR3 RAM, SPI, UART, I2C, PWM, ADC and 10/100 Ethernet. This SoC is ported on to Digilent Artix-7 100T, Nexys A7, Genesys2 FPGA development boards, extensively used by the Swadeshi Microprocessor Challenge Participants.

VEGA ecosystem

The proposed SoCs from CDAC will contain Single/Dual/Quad core processor as the core and integrated with in-house developed silicon proven peripheral IPs suitable for various applications like Strategic, Industrial, Automotive, Health, Consumer, etc. The complete ecosystem available for Embedded Systems design with the VEGA processors consists of Board Support Packages, SDK [14] with integrated tool chain, IDE plug-ins and Debugger for the development, testing and debugging. Linux and other standard Operating Systems have been ported and are also available as part of the ecosystem.[15][16][17]

Tapeouts

THEJAS32

THEAJS32 ASIC fabricated in SilTerra 130 nm technology which operates at a frequency of 100 MHz. THEJAS32 SoC includes VEGA ET1031 Microprocessor, 256KB internal SRAM, Three UARTs, Four SPIs, Three TIMERs, Eight PWMs, Three I2C interface, 32 GPIOs etc.[18][17]

References

  1. ↑ "CDAC all set to develop crucial technology indigenously". The Times of India. 30 March 2019. Retrieved 27 October 2021.
  2. ↑ "India to build 11 new supercomputers, with indigenous processors developed by C-DAC". The Print. 22 December 2019. Retrieved 27 October 2021.
  3. ↑ "India Preps RISC-V Processors". Retrieved 27 October 2021.
  4. ↑ "DESIGN AND IMPLEMENTATION OF A RISC-V ISA-BASED IN-ORDER DUAL ISSUE SUPERSCALAR PROCESSOR" (PDF). RISC-V Summit. 5 December 2018. Retrieved 27 October 2021.
  5. 1 2 3 Kaur, Roopmeet; Dash, Biswajeet; Shiney O, Jeba; Singh, Sukhpreet (19 July 2023). "Revolutionizing CanSat Technology with Vega Processors: A Comparative Study". 2023 2nd International Conference on Edge Computing and Applications (ICECAA): 1276–1282. doi:10.1109/ICECAA58104.2023.10212104. Retrieved 17 January 2024.
  6. ↑ "IIT Madras, CDAC jointly develop microprocessors". The Economic Times. 18 August 2020. Retrieved 27 October 2021.
  7. ↑ "स्वदेशी Microprocessor Challenge - Innovate Solutions for #आत्मनिर्भर भारत". My Gov India. Retrieved 27 October 2021.
  8. ↑ "Government launches Swadeshi Microprocessor Challenge". The Hindu BusinessLine. 18 August 2020. Retrieved 7 October 2021.
  9. ↑ "Swadeshi Microprocessor Challenge". PIB Delhi. 18 August 2020. Retrieved 27 October 2021.
  10. ↑ "Govt launches Rs 4.3 cr contest to develop tech products using indigenous microprocessors". Outlook. 18 August 2020. Retrieved 27 October 2021.
  11. ↑ Sharma, Devansh; Kumar, Ashish; Dhall, Aryan; Tomar, Riya; Pundir, Vikrant Singh; Bhandari, Hemant (November 2023). "fficient Parking & Toll Management: A RFID-Enabled Approach with Vega Aries Development Board" (PDF). International Journal of Innovative Science and Research Technology. 8 (11): 1559–1564. Retrieved 17 January 2024.
  12. ↑ "VEGA Processor Variants". Retrieved 22 October 2021.
  13. 1 2 "Thejas SoC's". VEGA Processors. Retrieved 27 October 2021.
  14. ↑ "C-DAC VEGA Processor". VEGA Processors. Retrieved 27 October 2021.
  15. ↑ "VEGA Ecosystem". VEGA Processors. Retrieved 27 October 2021.
  16. ↑ "Welcome to VEGA documentation". VEGA Processors. Retrieved 27 October 2021.
  17. 1 2 "VEGA Processors YouTube channel". VEGA Processors. Retrieved 27 October 2021.
  18. ↑ "Thejas SoC ASIC". VEGA Processors. Retrieved 7 April 2022.
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