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In computing, the Kogge–Stone adder (KSA or KS) is a parallel prefix form of carry-lookahead adder. Other parallel prefix adders (PPA) include the Sklansky adder (SA),[1] Brent–Kung adder (BKA),[2] the Han–Carlson adder (HCA),[3][4] the fastest known variation, the Lynch–Swartzlander spanning tree adder (STA),[5][6] Knowles adder (KNA)[7] and Beaumont-Smith adder (BSA).[8]
The Kogge–Stone adder takes more area to implement than the Brent–Kung adder, but has a lower fan-out at each stage, which increases performance for typical CMOS process nodes. However, wiring congestion is often a problem for Kogge–Stone adders. The Lynch–Swartzlander design is smaller, has lower fan-out, and does not suffer from wiring congestion; however to be used the process node must support Manchester carry chain implementations. The general problem of optimizing parallel prefix adders is identical to the variable block size, multi level, carry-skip adder optimization problem, a solution of which is found in Thomas Lynch's thesis of 1996.[6]
Design
Like all carry-lookahead adders, the Kogge-Stone adder internally tracks "generate" and "propagate" bits for spans of bits. We start with 1-bit spans, where a single column in the addition generates a carry bit if both inputs are 1 (logical AND), and propagates a carry bit if exactly one input is 1 (logical XOR). Then adjacent spans are merged together to produce generate and propagate bits for wider spans.
Merging continues until generate bits are known for all spans ending at the least significant bit, at which point these may be used as the carry inputs to compute all the sum bits in parallel.
The difference between different carry-lookahead adder designs lies in how the span merging takes place. Most designs use log2 n stages, doubling the width of the merged spans at each stage, but they differ in how spans which are not a power of two in size are divided into subspans. The Kogge–Stone design truncates the less-significant spans, and always uses full-width more-significant spans.
Stating with the 1-bit spans, all adjacent spans are merged to produce 2-bit spans. The least-significant span is treated specially: it is merged with the carry in to the addition, and it only produces a generate bit, as no propagation is possible. The next stage, each 2-bit wide span is merged with the preceding 2-bit span span to produce a 4-bit span. This is with the exception of the least significant three spans. The least significant span has already been computed, while the next two are merged with the carry in and the previously computed least significant span respectively, producing generate bits for 3- and 4-bit spans including the carry in.
This process repeats, doubling the span widths at each stage, and with simplified computation of least-significant spans, until all of the desired generate bits are known.
Since each span is merged with at most two other spans in the next stage (one more significant and one less significant), fan-out is minimal. However, there is significant wiring congestion; in the second-last stage of a 64-bit adder, the most significant half of the spans to be merged each require separate generate and propagate signals from spans 16 bits away, necessitating 32 horizontal wires across the adder. The final stage is similar; although only generate bits are needed, 32 of them are required to cross the adder.
Examples
An example of a 4-bit Kogge–Stone adder is shown in the diagram. Each vertical stage produces a "propagate" and a "generate" bit, as shown. The culminating generate bits (the carries) are produced in the last stage (vertically), and these bits are XOR'd with the initial propagate after the input (the red boxes) to produce the sum bits. E.g., the first (least-significant) sum bit is calculated by XORing the propagate in the farthest-right red box (a "1") with the carry-in (a "0"), producing a "1". The second bit is calculated by XORing the propagate in second box from the right (a "0") with C0 (a "0"), producing a "0".
4-bit Kogge-Stone adder, Radix-2, without Cin on Borland Turbo Basic 1.1:
'Step 0 P00 = A0 XOR B0 '1dt, S0, dt - delay time G00 = A0 AND B0 '1dt, C0 P10 = A1 XOR B1 '1dt G10 = A1 AND B1 '1dt P20 = A2 XOR B2 '1dt G20 = A2 AND B2 '1dt P30 = A3 XOR B3 '1dt G30 = A3 AND B3 '1dt 'Step 1, Distance=Radix^(Step-1)=2^0=1, valency-2 G11 = G10 OR (P10 AND G00) '3dt, C1 P21 = P20 AND P10 '2dt G21 = G20 OR (P20 AND G10) '3dt P31 = P30 AND P20 '2dt G31 = G30 OR (P30 AND G20) '3dt 'Step 2, Distance=Radix^(Step-1)=2^1=2, valency-2 G22 = G21 OR (P21 AND G00) '4dt, C2 G32 = G31 OR (P31 AND G11) '5dt, C3 'Sum S0 = P00 '1dt S1 = P10 XOR G00 '2dt S2 = P20 XOR G11 '4dt S3 = P30 XOR G22 '5dt S4 = G32 '5dt
4-bit PPA radix-4 (valency-2,3,4) adder (is 4-bit CLA radix-4 (valency-2,3,4) adder and 4-bit Sklansky radix-4 (valency-2,3,4) adder and 4-bit Kogge-Stone radix-4 (valency-2,3,4) adder and 4-bit Beaumont-Smith radix-4 (valency-2,3,4) adder):
'Step 0
P00 = A0 XOR B0 '1dt, S0
G00 = A0 AND B0 '1dt, C0
P10 = A1 XOR B1 '1dt
G10 = A1 AND B1 '1dt
P20 = A2 XOR B2 '1dt
G20 = A2 AND B2 '1dt
P30 = A3 XOR B3 '1dt
G30 = A3 AND B3 '1dt
'Step 1
G11 = G10 OR_
P10 AND G00 '3dt, C1, valency-2, distance-1
G21 = G20 OR_
P20 AND G10 OR_
P20 AND P10 AND G00 '3dt, C2, valency-3, distance-1,2
G31 = G30 OR_
P30 AND G20 OR_
P30 AND P20 AND G10 OR_
P30 AND P20 AND P10 AND G00 '3dt, C3, valency-4, distance-1,2,3
'Sum
S0 = P00 '1dt
S1 = P10 XOR G00 '2dt
S2 = P20 XOR G11 '4dt
S3 = P30 XOR G21 '4dt
S4 = G31 '3dt
4-bit Kogge-Stone adder, Radix-2, with Cin:
G0a = A0 AND Cin '1dt G0b = B0 AND Cin '1dt G0c = A0 AND B0 '1dt P00 = A0 XOR B0 '1dt G00 = G0a OR G0b OR G0c '2dt, C0 P10 = A1 XOR B1 '1dt G10 = A1 AND B1 '1dt P20 = A2 XOR B2 '1dt G20 = A2 AND B2 '1dt P30 = A3 XOR B3 '1dt G30 = A3 AND B3 '1dt G11 = G10 OR P10 AND G00 '4dt, C1 P21 = P20 AND P10 '2dt G21 = G20 OR P20 AND G10 '3dt P31 = P30 AND P20 '2dt G31 = G30 OR P30 AND G20 '3dt G22 = G21 OR P21 AND G00 '5dt, C2 G32 = G31 OR P31 AND G11 '6dt, C3, Cout S0 = P00 XOR Cin '2dt S1 = P10 XOR G00 '3dt S2 = P20 XOR G11 '5dt S3 = P30 XOR G22 '6dt
8-bit Kogge-Stone adder, radix-2, valency-2:
'---Step 0 P00 = A0 XOR B0 '1dt, S0 G00 = A0 AND B0 '1dt, C0 P10 = A1 XOR B1 '1dt G10 = A1 AND B1 '1dt P20 = A2 XOR B2 '1dt G20 = A2 AND B2 '1dt P30 = A3 XOR B3 '1dt G30 = A3 AND B3 '1dt P40 = A4 XOR B4 '1dt G40 = A4 AND B4 '1dt P50 = A5 XOR B5 '1dt G50 = A5 AND B5 '1dt P60 = A6 XOR B6 '1dt G60 = A6 AND B6 '1dt P70 = A7 XOR B7 '1dt G70 = A7 AND B7 '1dt '---Step 1 G11 = G10 OR (P10 AND G00) '3dt, C1 P21 = P20 AND P10 '2dt G21 = G20 OR (P20 AND G10) '3dt P31 = P30 AND P20 '2dt G31 = G30 OR (P30 AND G20) '3dt P41 = P40 AND P30 '2dt G41 = G40 OR (P40 AND G30) '3dt P51 = P50 AND P40 '2dt G51 = G50 OR (P50 AND G40) '3dt P61 = P60 AND P50 '2dt G61 = G60 OR (P60 AND G50) '3dt P71 = P70 AND P60 '2dt G71 = G70 OR (P70 AND G60) '3dt '---Step 2 G22 = G21 OR (P21 AND G00) '4dt, C2 G32 = G31 OR (P31 AND G11) '5dt, C3 P42 = P41 AND P21 '3dt G42 = G41 OR (P41 AND G21) '5dt P52 = P51 AND P31 '3dt G52 = G51 OR (P51 AND G31) '5dt P62 = P61 AND P41 '3dt G62 = G61 OR (P61 AND G41) '5dt P72 = P71 AND P51 '3dt G72 = G71 OR (P71 AND G51) '5dt '---Step 3 G43 = G42 OR P42 AND G00 '6dt, C4 G53 = G52 OR P52 AND G11 '6dt, C5 G63 = G62 OR P62 AND G22 '6dt, C6 G73 = G72 OR P72 AND G32 '7dt, C7, Cout '---Sum S0 = P00 '1dt S1 = P10 XOR G00 '2dt S2 = P20 XOR G11 '4dt S3 = P30 XOR G22 '5dt S4 = P40 XOR G32 '6dt S5 = P50 XOR G43 '7dt S6 = P60 XOR G53 '7dt S7 = P70 XOR G63 '7dt S8 = G73 '7dt
8-bit Kogge-Stone adder, radix-4, valency-2,3,4:
P00 = A0 XOR B0 '1dt, S0
G00 = A0 AND B0 '1dt, C0
P10 = A1 XOR B1 '1dt
G10 = A1 AND B1 '1dt
P20 = A2 XOR B2 '1dt
G20 = A2 AND B2 '1dt
P30 = A3 XOR B3 '1dt
G30 = A3 AND B3 '1dt
P40 = A4 XOR B4 '1dt
G40 = A4 AND B4 '1dt
P50 = A5 XOR B5 '1dt
G50 = A5 AND B5 '1dt
P60 = A6 XOR B6 '1dt
G60 = A6 AND B6 '1dt
P70 = A7 XOR B7 '1dt
G70 = A7 AND B7 '1dt
G11 = G10 OR P10 AND G00 '3dt, C1, valency-2, distance=4^0=1
G21 = G20 OR_
P20 AND G10 OR_
P20 AND P10 AND G00 '3dt, C2, valency-3, distance-1,2
G31 = G30 OR_
P30 AND G20 OR_
P30 AND P20 AND G10 OR_
P30 AND P20 AND P10 AND G00 '3dt, C3, valency-4, distance-1,2,3
P41 = P40 AND P30 AND P20 AND P10 '2dt, valency-4, distance-1,2,3
G41 = G40 OR_
P40 AND G30 OR_
P40 AND P30 AND G20 OR_
P40 AND P30 AND P20 AND G10 '3dt, valency-4, distance-1,2,3
P51 = P50 AND P40 AND P30 AND P20 '2dt, valency-4, distance-1,2,3
G51 = G50 OR_
P50 AND G40 OR_
P50 AND P40 AND G30 OR_
P50 AND P40 AND P30 AND G20 '3dt, valency-4, distance-1,2,3
P61 = P60 AND P50 AND P40 AND P30 '2dt, valency-4, distance-1,2,3
G61 = G60 OR_
P60 AND G50 OR_
P60 AND P50 AND G40 OR_
P60 AND P50 AND P40 AND G30 '3dt, valency-4, distance-1,2,3
P71 = P70 AND P60 AND P50 AND P40 '2dt, valency-4, distance-1,2,3
G71 = G70 OR_
P70 AND G60 OR_
P70 AND P60 AND G50 OR_
P70 AND P60 AND P50 AND G40 '3dt, valency-4, distance-1,2,3
'valency=2, distance=4^1=4
G42 = G41 OR P41 AND G00 '5dt, C4
G52 = G51 OR P51 AND G11 '5dt, C5
G62 = G61 OR P61 AND G21 '5dt, C6
G72 = G71 OR P71 AND G31 '5dt, C7
S0 = P00 '1dt
S1 = P10 XOR G00 '2dt
S2 = P20 XOR G11 '4dt
S3 = P30 XOR G21 '4dt
S4 = P40 XOR G31 '6dt
S5 = P50 XOR G42 '6dt
S6 = P60 XOR G52 '6dt
S7 = P70 XOR G62 '6dt
8-bit PPA valency-2,3,4,5,6,7,8 adder (is 8-bit CLA valency-2,3,4,5,6,7,8 adder and 8-bit Sklansky valency-2,3,4,5,6,7,8 adder and 8-bit Kogge-Stone valency-2,3,4,5,6,7,8 adder):
P00 = A0 XOR B0 '1dt, S0
G00 = A0 AND B0 '1dt, C0
P10 = A1 XOR B1 '1dt
G10 = A1 AND B1 '1dt
P20 = A2 XOR B2 '1dt
G20 = A2 AND B2 '1dt
P30 = A3 XOR B3 '1dt
G30 = A3 AND B3 '1dt
P40 = A4 XOR B4 '1dt
G40 = A4 AND B4 '1dt
P50 = A5 XOR B5 '1dt
G50 = A5 AND B5 '1dt
P60 = A6 XOR B6 '1dt
G60 = A6 AND B6 '1dt
P70 = A7 XOR B7 '1dt
G70 = A7 AND B7 '1dt
'------------------------------------------
G11 = G10 OR P10 AND G00 '3dt, C1, valency-2, distance-1
G21 = G20 OR_ '3dt, C2, valency-3, distance-1,2
P20 AND G10 OR_
P20 AND P10 AND G00
G31 = G30 OR_ '3dt, C3, valency-4, distance-1,2,3
P30 AND G20 OR_
P30 AND P20 AND G10 OR_
P30 AND P20 AND P10 AND G00
G41 = G40 OR_ '3dt, C4, valency-5, distance-1,2,3,4
P40 AND G30 OR_
P40 AND P30 AND G20 OR_
P40 AND P30 AND P20 AND G10 OR_
P40 AND P30 AND P20 AND P10 AND G00
G51 = G50 OR_ '3dt, C5, valency-6, distance-1,2,3,4,5
P50 AND G40 OR_
P50 AND P40 AND G30 OR_
P50 AND P40 AND P30 AND G20 OR_
P50 AND P40 AND P30 AND P20 AND G10 OR_
P50 AND P40 AND P30 AND P20 AND P10 AND G00
G61 = G60 OR_ '3dt, C6, valency-7, distance-1,2,3,4,5,6
P60 AND G50 OR_
P60 AND P50 AND G40 OR_
P60 AND P50 AND P40 AND G30 OR_
P60 AND P50 AND P40 AND P30 AND G20 OR_
P60 AND P50 AND P40 AND P30 AND P20 AND G10 OR_
P60 AND P50 AND P40 AND P30 AND P20 AND P10 AND G00
G71 = G70 OR_ '3dt, C7, valency-8, distance-1,2,3,4,5,6,7
P70 AND G60 OR_
P70 AND P60 AND G50 OR_
P70 AND P60 AND P50 AND G40 OR_
P70 AND P60 AND P50 AND P40 AND G30 OR_
P70 AND P60 AND P50 AND P40 AND P30 AND G20 OR_
P70 AND P60 AND P50 AND P40 AND P30 AND P20 AND G10 OR_
P70 AND P60 AND P50 AND P40 AND P30 AND P20 AND P10 AND G00
'--------------------------------------
S0 = P00 '1dt
S1 = P10 XOR G00 '2dt
S2 = P20 XOR G11 '4dt
S3 = P30 XOR G21 '4dt
S4 = P40 XOR G31 '4dt
S5 = P50 XOR G41 '4dt
S6 = P60 XOR G51 '4dt
S7 = P70 XOR G61 '4dt
8-bit PPA valency-2,3,4,5,6,7,8 adder:
P00 = A0 XOR B0 '1dt, S0
G00 = A0 AND B0 '1dt, C0
P10 = A1 XOR B1 '1dt
G10 = A1 AND B1 '1dt
P20 = A2 XOR B2 '1dt
G20 = A2 AND B2 '1dt
P30 = A3 XOR B3 '1dt
G30 = A3 AND B3 '1dt
P40 = A4 XOR B4 '1dt
G40 = A4 AND B4 '1dt
P50 = A5 XOR B5 '1dt
G50 = A5 AND B5 '1dt
P60 = A6 XOR B6 '1dt
G60 = A6 AND B6 '1dt
P70 = A7 XOR B7 '1dt
G70 = A7 AND B7 '1dt
S1 = P10 XOR G00
S2 = P20 XOR G10 OR P10 AND G00 '4dt, valency-2, distance-1
S3 = P30 XOR G20 OR_ '4dt, valency-3, distance-1,2
P20 AND G10 OR_
P20 AND P10 AND G00
S4 = P40 XOR G30 OR_ '4dt, valency-4, distance-1,2,3
P30 AND G20 OR_
P30 AND P20 AND G10 OR_
P30 AND P20 AND P10 AND G00
S5 = P50 XOR G40 OR_ '4dt, valency-5, distance-1,2,3,4
P40 AND G30 OR_
P40 AND P30 AND G20 OR_
P40 AND P30 AND P20 AND G10 OR_
P40 AND P30 AND P20 AND P10 AND G00
S6 = P60 XOR G50 OR_ '4dt, valency-6, distance-1,2,3,4,5
P50 AND G40 OR_
P50 AND P40 AND G30 OR_
P50 AND P40 AND P30 AND G20 OR_
P50 AND P40 AND P30 AND P20 AND G10 OR_
P50 AND P40 AND P30 AND P20 AND P10 AND G00
S7 = P70 XOR G60 OR_ '4dt, valency-7, distance-1,2,3,4,5,6
P60 AND G50 OR_
P60 AND P50 AND G40 OR_
P60 AND P50 AND P40 AND G30 OR_
P60 AND P50 AND P40 AND P30 AND G20 OR_
P60 AND P50 AND P40 AND P30 AND P20 AND G10 OR_
P60 AND P50 AND P40 AND P30 AND P20 AND P10 AND G00
G71 = G70 OR_ '3dt, C7, valency-8, distance-1,2,3,4,5,6,7
P70 AND G60 OR_
P70 AND P60 AND G50 OR_
P70 AND P60 AND P50 AND G40 OR_
P70 AND P60 AND P50 AND P40 AND G30 OR_
P70 AND P60 AND P50 AND P40 AND P30 AND G20 OR_
P70 AND P60 AND P50 AND P40 AND P30 AND P20 AND G10 OR_
P70 AND P60 AND P50 AND P40 AND P30 AND P20 AND P10 AND G00
The Kogge-Stone adder concept was developed by Peter M. Kogge and Harold S. Stone, who published it in a seminal 1973 paper titled A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations.[9]
Enhancements
Enhancements to the original implementation include increasing the radix and sparsity of the adder. The radix of the adder refers to how many results from the previous level of computation are used to generate the next one. The original implementation uses radix-2, although it's possible to create radix-4 and higher. Doing so increases the power and delay of each stage, but reduces the number of required stages. In the so-called sparse Kogge–Stone adder (SKA) the sparsity of the adder refers to how many carry bits are generated by the carry-tree. Generating every carry bit is called sparsity-1, whereas generating every other is sparsity-2 and every fourth is sparsity-4. The resulting carries are then used as the carry-in inputs for much shorter ripple carry adders or some other adder design, which generates the final sum bits. Increasing sparsity reduces the total needed computation and can reduce the amount of routing congestion.
Above is an example of a Kogge–Stone adder with sparsity-4. Elements eliminated by sparsity shown marked with transparency. As shown, power and area of the carry generation is improved significantly, and routing congestion is substantially reduced. Each generated carry feeds a multiplexer for a carry select adder or the carry-in of a ripple carry adder.
16-bit Kogge-Stone adder valency-2 without Cin:
P00 = A0 XOR B0 '1dt, S0, dt - type delay time G00 = A0 AND B0 '1dt, C0 P10 = A1 XOR B1 '1dt G10 = A1 AND B1 '1dt P20 = A2 XOR B2 '1dt G20 = A2 AND B2 '1dt P30 = A3 XOR B3 '1dt G30 = A3 AND B3 '1dt P40 = A4 XOR B4 '1dt G40 = A4 AND B4 '1dt P50 = A5 XOR B5 '1dt G50 = A5 AND B5 '1dt P60 = A6 XOR B6 '1dt G60 = A6 AND B6 '1dt P70 = A7 XOR B7 '1dt G70 = A7 AND B7 '1dt P80 = A8 XOR B8 '1dt G80 = A8 AND B8 '1dt P90 = A9 XOR B9 '1dt G90 = A9 AND B9 '1dt P100 = A10 XOR B10 '1dt G100 = A10 AND B10 '1dt P110 = A11 XOR B11 '1dt G110 = A11 AND B11 '1dt P120 = A12 XOR B12 '1dt G120 = A12 AND B12 '1dt P130 = A13 XOR B13 '1dt G130 = A13 AND B13 '1dt P140 = A14 XOR B14 '1dt G140 = A14 AND B14 '1dt P150 = A15 XOR B15 '1dt G150 = A15 AND B15 '1dt G11 = G10 OR P10 AND G00 '3dt, C1 P21 = P20 AND P10 '2dt G21 = G20 OR P20 AND G10 '3dt P31 = P30 AND P20 '2dt G31 = G30 OR P30 AND G20 '3dt P41 = P40 AND P30 '2dt G41 = G40 OR P40 AND G30 '3dt P51 = P50 AND P40 '2dt G51 = G50 OR P50 AND G40 '3dt P61 = P60 AND P50 '2dt G61 = G60 OR P60 AND G50 '3dt P71 = P70 AND P60 '2dt G71 = G70 OR P70 AND G60 '3dt P81 = P80 AND P70 '2dt G81 = G80 OR P80 AND G70 '3dt P91 = P90 AND P80 '2dt G91 = G90 OR P90 AND G80 '3dt P101 = P100 AND P90 '2dt G101 = G100 OR P100 AND G90 '3dt P111 = P110 AND P100 '2dt G111 = G110 OR P110 AND G100 '3dt P121 = P120 AND P110 '2dt G121 = G120 OR P120 AND G110 '3dt P131 = P130 AND P120 '2dt G131 = G130 OR P130 AND G120 '3dt P141 = P140 AND P130 '2dt G141 = G140 OR P140 AND G130 '3dt P151 = P150 AND P140 '2dt G151 = G150 OR P150 AND G140 '3dt G22 = G21 OR P21 AND G00 '4dt, C2 G32 = G31 OR P31 AND G11 '5dt, C3 P42 = P41 AND P21 '3dt G42 = G41 OR P41 AND G21 '5dt P52 = P51 AND P31 '3dt G52 = G51 OR P51 AND G31 '5dt P62 = P61 AND P41 '3dt G62 = G61 OR P61 AND G41 '5dt P72 = P71 AND P51 '3dt G72 = G71 OR P71 AND G51 '5dt P82 = P81 AND P61 '3dt G82 = G81 OR P81 AND G61 '5dt P92 = P91 AND P71 '3dt G92 = G91 OR P91 AND G71 '5dt P102 = P101 AND P81 '3dt G102 = G101 OR P101 AND G81 '5dt P112 = P111 AND P91 '3dt G112 = G111 OR P111 AND G91 '5dt P122 = P121 AND P101 '3dt G122 = G121 OR P121 AND G101 '5dt P132 = P131 AND P111 '3dt G132 = G131 OR P131 AND G111 '5dt P142 = P141 AND P121 '3dt G142 = G141 OR P141 AND G121 '5dt P152 = P151 AND P131 '3dt G152 = G151 OR P151 AND G131 '5dt G43 = G42 OR P42 AND G00 '6dt, C4 G53 = G52 OR P52 AND G11 '6dt, C5 G63 = G62 OR P62 AND G22 '6dt, C6 G73 = G72 OR P72 AND G32 '7dt, C7 P83 = P82 AND P42 '4dt G83 = G82 OR P82 AND G42 '7dt P93 = P92 AND P52 '4dt G93 = G92 OR P92 AND G52 '7dt P103 = P102 AND P62 '4dt G103 = G102 OR P102 AND G62 '7dt P113 = P112 AND P72 '4dt G113 = G112 OR P112 AND G72 '7dt P123 = P122 AND P82 '4dt G123 = G122 OR P122 AND G82 '7dt P133 = P132 AND P92 '4dt G133 = G132 OR P132 AND G92 '7dt P143 = P142 AND P102 '4dt G143 = G142 OR P142 AND G102 '7dt P153 = P152 AND P112 '4dt G153 = G152 OR P152 AND G112 '7dt G84 = G83 OR P83 AND G00 '8dt, C8 G94 = G93 OR P93 AND G11 '8dt, C9 G104 = G103 OR P103 AND G22 '8dt, C10 G114 = G113 OR P113 AND G32 '8dt, C11 G124 = G123 OR P123 AND G43 '8dt, C12 G134 = G133 OR P133 AND G53 '8dt, C13 G144 = G143 OR P143 AND G63 '8dt, C14 G154 = G153 OR P153 AND G73 '9dt, C15 S0 = P00 '1dt S1 = P10 XOR G00 '2dt S2 = P20 XOR G11 '4dt S3 = P30 XOR G22 '5dt S4 = P40 XOR G32 '6dt S5 = P50 XOR G43 '7dt S6 = P60 XOR G53 '7dt S7 = P70 XOR G63 '7dt S8 = P80 XOR G73 '8dt S9 = P90 XOR G84 '9dt S10 = P100 XOR G94 '9dt S11 = P110 XOR G104 '9dt S12 = P120 XOR G114 '9dt S13 = P130 XOR G124 '9dt S14 = P140 XOR G134 '9dt S15 = P150 XOR G144 '9dt
References
- ↑ Conditional-Sum Addition Logic. Sklansky J. IRE Transaction on Electronic Computer. 1960. p.226.
- ↑ Brent, Richard Peirce; Kung, Hsiang Te (March 1982). "A Regular Layout for Parallel Adders" (PDF). IEEE Transactions on Computers. C-31 (3): 260–264. doi:10.1109/TC.1982.1675982. ISSN 0018-9340. S2CID 17348212. Archived from the original on September 24, 2017.
- ↑ Han, Tackdon; Carlson, David A.; Levitan, Steven P. (October 1982). "VLSI design of high-speed, low-area addition circuitry". Proceedings 1981 IEEE International Conference on Computer Design: VLSI in Computers & Processors. IEEE: 418–422. ISBN 0-81860802-1.
- ↑ Han, Tackdon; Carlson, David A. (October 1987). "Fast area-efficient VLSI adders". Proceedings 8th Symposium on Computer Arithmetic. IEEE: 49–56.
- ↑ Lynch, Thomas Walker; Swartzlander, Jr., Earl E. (August 1992). "A spanning tree carry lookahead adder". IEEE Transactions on Computers. 41 (8): 931–939. doi:10.1109/12.156535.
- 1 2 Lynch, Thomas Walker (May 1996). "Binary Adders" (Thesis). University of Texas. Archived (PDF) from the original on 2018-04-14. Retrieved 2018-04-14.
- ↑ A Family of Adders. Simon Knowles. Element 14, Aztec Centre, Bristol, UK.
- ↑ Parallel Prefix Adder Desine. Beaumont-Smith A., Cheng-Chew L. Department of Electrical and Electronic Engineering, The University of Adelaide, Australia. 2001
- ↑ Kogge, Peter Michael; Stone, Harold S. (August 1973). "A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations". IEEE Transactions on Computers. C-22 (8): 786–793. doi:10.1109/TC.1973.5009159. S2CID 206619926.
Further reading
- Zeydel, Bart R. (2006). "Energy-Delay Characteristics of CMOS Adders". In Oklobdzija, Vojin G.; Krishnamurth, Ram K. (eds.). High-Performance Energy-Efficient Microprocessor Design. Series on Integrated Circuits and Systems. Dordrecht, Netherlands: Springer. pp. 147–169. doi:10.1007/978-0-387-34047-0_6. ISBN 0-387-28594-6.