A carry-lookahead adder (CLA) or fast adder is a type of electronics adder used in digital logic. A carry-lookahead adder improves speed by reducing the amount of time required to determine carry bits. It can be contrasted with the simpler, but usually slower, ripple-carry adder (RCA), for which the carry bit is calculated alongside the sum bit, and each stage must wait until the previous carry bit has been calculated to begin calculating its own sum bit and carry bit. The carry-lookahead adder calculates one or more carry bits before the sum, which reduces the wait time to calculate the result of the larger-value bits of the adder.

Already in the mid-1800s, Charles Babbage recognized the performance penalty imposed by the ripple-carry used in his Difference Engine, and subsequently designed mechanisms for anticipating carriage for his never-built Analytical Engine.^[1][2] Konrad Zuse is thought to have implemented the first carry-lookahead adder in his 1930s binary mechanical computer, the Zuse Z1.^[3] Gerald B. Rosenberger of IBM filed for a patent on a modern binary carry-lookahead adder in 1957.^[4]

Two widely used implementations of the concept are the Kogge–Stone adder (KSA) and Brent–Kung adder (BKA).

Theory of operation

Carry lookahead method

Carry-lookahead logic uses the concepts of generating and propagating carries. Although in the context of a carry-lookahead adder, it is most natural to think of generating and propagating in the context of binary addition, the concepts can be used more generally than this. In the descriptions below, the word digit can be replaced by bit when referring to binary addition of 2.

The addition of two 1-digit inputs A and B is said to generate if the addition will always carry, regardless of whether there is an input-carry (equivalently, regardless of whether any less significant digits in the sum carry). For example, in the decimal addition 52 + 67, the addition of the tens digits 5 and 6 generates because the result carries to the hundreds digit regardless of whether the ones digit carries; in the example, the ones digit does not carry (2 + 7 = 9). Even if the numbers were, say, 54 and 69, the addition of the tens digits 5 and 6 would still generate because the result once again carries to the hundreds digit despite 4 and 9 creating a carrying.

In the case of binary addition, ${\displaystyle A+B}$ generates if and only if both A and B are 1. If we write ${\displaystyle G(A,B)}$ to represent the binary predicate that is true if and only if ${\displaystyle A+B}$ generates, we have

${\displaystyle G(A,B)=A\cdot B}$

where ${\displaystyle A\cdot B}$ is a logical conjunction (i.e., an and).

The addition of two 1-digit inputs A and B is said to propagate if the addition will carry whenever there is an input carry (equivalently, when the next less significant digit in the sum carries). For example, in the decimal addition 37 + 62, the addition of the tens digits 3 and 6 propagate because the result would carry to the hundreds digit if the ones were to carry (which in this example, it does not). Note that propagate and generate are defined with respect to a single digit of addition and do not depend on any other digits in the sum.

In the case of binary addition, ${\displaystyle A+B}$ propagates if and only if at least one of A or B is 1. If ${\displaystyle P(A,B)}$ is written to represent the binary predicate that is true if and only if ${\displaystyle A+B}$ propagates, one has

${\displaystyle P(A,B)=A+B}$

where ${\displaystyle A+B}$ on the right-hand side of the equation is a logical disjunction (i.e., an or).

Sometimes a slightly different definition of propagate is used. By this definition A + B is said to propagate if the addition will carry whenever there is an input carry, but will not carry if there is no input carry. Due to the way generate and propagate bits are used by the carry-lookahead logic, it doesn't matter which definition is used. In the case of binary addition, this definition is expressed by

${\displaystyle P'(A,B)=A\oplus B}$

where ${\displaystyle A\oplus B}$ is an exclusive or (i.e., an xor).

${\displaystyle A}$	${\displaystyle B}$	${\displaystyle C_{i}}$	${\displaystyle C_{o}}$	Type of Carry
0	0	0	0	None
0	0	1	0	None
0	1	0	0	None
0	1	1	1	Propagate
1	0	0	0	None
1	0	1	1	Propagate
1	1	0	1	Generate
1	1	1	1	Generate/Propagate

Table showing when carries are propagated or generated.

For binary arithmetic, or is faster than xor and takes fewer transistors to implement. However, for a multiple-level carry-lookahead adder, it is simpler to use ${\displaystyle P'(A,B)}$.

Given these concepts of generate and propagate, a digit of addition carries precisely when either the addition generates or the next less significant bit carries and the addition propagates. Written in boolean algebra, with ${\displaystyle C_{i}}$ the carry bit of digit i, and ${\displaystyle P_{i}}$ and ${\displaystyle G_{i}}$ the propagate and generate bits of digit i respectively,

${\displaystyle C_{i+1}=G_{i}+(P_{i}\cdot C_{i}).}$

Implementation details

A partial full adder, with propagate and generate outputs.

Logic gate implementation of a 4-bit carry lookahead adder.

A block diagram of a 4-bit carry lookahead adder.

For each bit in a binary sequence to be added, the carry-lookahead logic will determine whether that bit pair will generate a carry or propagate a carry. This allows the circuit to "pre-process" the two numbers being added to determine the carry ahead of time. Then, when the actual addition is performed, there is no delay from waiting for the ripple-carry effect (or time it takes for the carry from the first full adder to be passed down to the last full adder).

To determine whether a bit pair will generate a carry, the following logic works:

${\displaystyle G_{i}=A_{i}\cdot B_{i}}$

To determine whether a bit pair will propagate a carry, either of the following logic statements work:

${\displaystyle P_{i}=A_{i}\oplus B_{i}}$

${\displaystyle P_{i}=A_{i}+B_{i}}$

The reason why this works is based on evaluation of ${\displaystyle C_{1}=G_{0}+P_{0}\cdot C_{0}}$. The only difference in the truth tables between (${\displaystyle A\oplus B}$) and (${\displaystyle A+B}$) is when both ${\displaystyle A}$ and ${\displaystyle B}$ are 1. However, if both ${\displaystyle A}$ and ${\displaystyle B}$ are 1, then the ${\displaystyle G_{0}}$ term is 1 (since its equation is ${\displaystyle A\cdot B}$), and the ${\displaystyle P_{0}\cdot C_{0}}$ term becomes irrelevant. The XOR is used normally within a basic full adder circuit; the OR is an alternative option (for a carry-lookahead only), which is far simpler in transistor-count terms.

For the example provided, the logic for the generate (${\displaystyle G}$) and propagate (${\displaystyle P}$) values are given below. The numeric value determines the signal from the circuit above, starting from 0 on the far right to 3 on the far left:

${\displaystyle C_{1}=G_{0}+P_{0}\cdot C_{0}}$

${\displaystyle C_{2}=G_{1}+P_{1}\cdot C_{1}}$

${\displaystyle C_{3}=G_{2}+P_{2}\cdot C_{2}}$

${\displaystyle C_{4}=G_{3}+P_{3}\cdot C_{3}}$

Substituting ${\displaystyle C_{1}}$ into ${\displaystyle C_{2}}$, then ${\displaystyle C_{2}}$ into ${\displaystyle C_{3}}$, then ${\displaystyle C_{3}}$ into ${\displaystyle C_{4}}$ yields the following expanded equations:

${\displaystyle C_{1}=G_{0}+P_{0}\cdot C_{0}}$

${\displaystyle C_{2}=G_{1}+G_{0}\cdot P_{1}+C_{0}\cdot P_{0}\cdot P_{1}}$

${\displaystyle C_{3}=G_{2}+G_{1}\cdot P_{2}+G_{0}\cdot P_{1}\cdot P_{2}+C_{0}\cdot P_{0}\cdot P_{1}\cdot P_{2}}$

${\displaystyle C_{4}=G_{3}+G_{2}\cdot P_{3}+G_{1}\cdot P_{2}\cdot P_{3}+G_{0}\cdot P_{1}\cdot P_{2}\cdot P_{3}+C_{0}\cdot P_{0}\cdot P_{1}\cdot P_{2}\cdot P_{3}}$

The carry-lookahead 4-bit adder can also be used in a higher-level circuit by having each CLA logic circuit produce a propagate and generate signal to a higher-level CLA logic circuit. The group propagate (${\displaystyle PG}$) and group generate (${\displaystyle GG}$) for a 4-bit CLA are:

${\displaystyle PG=P_{0}\cdot P_{1}\cdot P_{2}\cdot P_{3}}$

${\displaystyle GG=G_{3}+G_{2}\cdot P_{3}+G_{1}\cdot P_{3}\cdot P_{2}+G_{0}\cdot P_{3}\cdot P_{2}\cdot P_{1}}$

They can then be used to create a carry-out for that particular 4-bit group:

${\displaystyle CG=GG+PG\cdot C_{in}}$

It can be seen that this is equivalent to ${\displaystyle C_{4}}$ in previous equations.

Putting four 4-bit CLAs together yields four group propagates and four group generates. A lookahead-carry unit (LCU) takes these 8 values and uses identical logic to calculate ${\displaystyle C_{i}}$ in the CLAs. The LCU then generates the carry input for each of the 4 CLAs and a fifth equal to ${\displaystyle C_{16}}$.

The calculation of the gate delay of a 16-bit adder (using 4 CLAs and 1 LCU) is not as straight forward as the ripple carry adder.

Starting at time of zero:

• calculation of ${\displaystyle P_{i}}$ and ${\displaystyle G_{i}}$ is done at time 1,
• calculation of the ${\displaystyle PG}$ is done at time 2,
• calculation of the ${\displaystyle GG}$ is done at time 3,
• calculation of the inputs for the CLAs from the LCU are done at:
  • time 0 for the first CLA,
  • time 5 for the second, third and fourth CLA,
• calculation of the ${\displaystyle S_{i}}$ are done at:
  • time 4 for the first CLA,
  • time 8 for the second, third & fourth CLA,
• calculation of the final carry bit (${\displaystyle C_{16}}$) is done at time 5.

The maximal time is 8 gate delays (for ${\displaystyle S_{[8-15]}}$).

A standard 16-bit ripple-carry adder would take 16 × 3 − 1 = 47 gate delays.

Expansion

This example is a 4-bit carry look ahead adder, there are 5 outputs. Below is the expansion:

S0 = (A0 XOR B0) XOR Cin                               '2dt (dt - delay time)

S1 = (A1 XOR B1)
     XOR ((A0 AND B0)
      OR ((A0 XOR B0) AND Cin))                                          '4dt  

S2 = (A2 XOR B2)
     XOR ((A1 AND B1)
      OR ((A1 XOR B1) AND (A0 AND B0))
      OR ((A1 XOR B1) AND (A0 XOR B0) AND Cin))                          '4dt

S3 = (A3 XOR B3)
     XOR ((A2 AND B2)
      OR ((A2 XOR B2) AND (A1 AND B1))
      OR ((A2 XOR B2) AND (A1 XOR B1) AND (A0 AND B0))
      OR ((A2 XOR B2) AND (A1 XOR B1) AND (A0 XOR B0) AND Cin))          '4dt

Cout = (A3 AND B3)
       OR ((A3 XOR B3) AND (A2 AND B2))
       OR ((A3 XOR B3) AND (A2 XOR B2) AND (A1 AND B1))
       OR ((A3 XOR B3) AND (A2 XOR B2) AND (A1 XOR B1) AND (A0 AND B0))
       OR ((A3 XOR B3) AND (A2 XOR B2) AND (A1 XOR B1) AND (A0 XOR B0) AND Cin)  '3dt

More simple 4-bit carry-lookahead adder:

'Step 0
Gin = Cin                                   '0dt
P00 = A0 XOR B0                             '1dt
G00 = A0 AND B0                             '1dt
P10 = A1 XOR B1                             '1dt
G10 = A1 AND B1                             '1dt
P20 = A2 XOR B2                             '1dt
G20 = A2 AND B2                             '1dt
P30 = A3 XOR B3                             '1dt
G30 = A3 AND B3                             '1dt
'Step 1
G01 = G00 OR_
      P00 AND Gin                           '3dt, C0, valency-2
G11 = G10 OR_
      P10 AND G00 OR_
      P10 AND P00 AND Gin                   '3dt, C1, valency-3
G21 = G20 OR_
      P20 AND G10 OR_
      P20 AND P10 AND G00 OR_
      P20 AND P10 AND P00 AND Gin           '3dt, C2, valency-4
G31 = G30 OR_
      P30 AND G20 OR_
      P30 AND P20 AND G10 OR_
      P30 AND P20 AND P10 AND G00 OR_
      P30 AND P20 AND P10 AND P00 AND Gin   '3dt, C3, valency-5
'Sum
S0 = P00 XOR Gin                            '2dt
S1 = P10 XOR G01                            '4dt
S2 = P20 XOR G11                            '4dt
S3 = P30 XOR G21                            '4dt
S4 =         G31                            '3dt, Cout

Manchester carry chain

The Manchester carry chain is a variation of the carry-lookahead adder^[5] that uses shared logic to lower the transistor count. As can be seen above in the implementation section, the logic for generating each carry contains all of the logic used to generate the previous carries. A Manchester carry chain generates the intermediate carries by tapping off nodes in the gate that calculates the most significant carry value. However, not all logic families have these internal nodes, CMOS being a major example. Dynamic logic can support shared logic, as can transmission gate logic. One of the major downsides of the Manchester carry chain is that the capacitive load of all of these outputs, together with the resistance of the transistors causes the propagation delay to increase much more quickly than a regular carry lookahead. A Manchester-carry-chain section generally doesn't exceed 4 bits.

See also

• Carry-skip adder
• Carry operator
• Speculative execution

References

Further reading

• Hardware algorithms for arithmetic modules, ARITH research group, Aoki lab., Tohoku University
• Katz, Randy (1994). Contemporary Logic Design. Vol. 26. The Benjamin/Cummings Publishing Company. pp. 249–256. doi:10.1016/0026-2692(95)90052-7. ISBN 0-8053-2703-7. {{cite book}}: |journal= ignored (help)
• Savard, John J. G. (2018) [2006]. "Advanced Arithmetic Techniques". quadibloc. Archived from the original on 2018-07-03. Retrieved 2018-07-16.

External links

• Carry Look Ahead Adder JavaScript simulator