The MERSI protocol is a cache coherency and memory coherence protocol used by the PowerPC G4.[1] The protocol consists of five states, Modified (M), Exclusive (E), Read Only or Recent (R), Shared (S) and Invalid (I). The M, E, S and I states are the same as in the MESI protocol. The R state is similar to the E state in that it is constrained to be the only clean, valid, copy of that data in the computer system. Unlike the E state, the processor is required to initially request ownership of the cache line in the R state before the processor may modify the cache line and transition to the M state. In both the MESI and MERSI protocols, the transition from the E to M is silent.[2]

For any given pair of caches, the permitted states of a given cache line are as follows:

 M  E  R  S  I 
 M  Red XRed XRed XRed XGreen tick
 E  Red XRed XRed XRed XGreen tick
 R  Red XRed XRed XRed XGreen tick
 S  Red XRed XRed XGreen tickGreen tick
 I  Green tickGreen tickGreen tickGreen tickGreen tick

References

  1. ↑ Nicoletta, C.; Alvarez, J.; Barkin, E.; Chai-Chin Chao; Johnson, B. R.; Lassandro, F. M.; Patel, P.; Reid, D.; Sanchez, H.; Seigel, J.; Snyder, M.; Sullivan, S.; Taylor, S. A.; Minh Vo (November 1999). "A 450-MHz RISC microprocessor with enhanced instruction set and copper interconnect". IEEE Journal of Solid-State Circuits. 34 (11): 1478–1491. Bibcode:1999IJSSC..34.1478N. doi:10.1109/4.799852.
  2. ↑ US Patent 6857051, http://www.google.com/patents/about?id=ZtsVAAAAEBAJ&dq=6857051
This article is issued from Wikipedia. The text is licensed under Creative Commons - Attribution - Sharealike. Additional terms may apply for the media files.