30-pin, proprietary Apple 68-pin, and 72-pin SIMMs

A SIMM (single in-line memory module) is a type of memory module containing random-access memory used in computers from the early 1980s to the early 2000s. It differs from a dual in-line memory module (DIMM), the most predominant form of memory module since the late 1990s, in that the contacts on a SIMM are redundant on both sides of the module. SIMMs were standardised under the JEDEC JESD-21C standard.

Most early PC motherboards (8088-based PCs, XTs, and early ATs) used socketed DIP chips for DRAM. As computer memory capacities grew, memory modules were used to save motherboard space and ease memory expansion. Instead of plugging in eight or nine single DIP chips, only one additional memory module was needed to increase the memory of the computer.

History

SIMMs were invented in 1983 by James E. Clayton[1] at Wang Laboratories with subsequent patents granted in 1987.[2] [3] Wang Laboratories litigated both patents against multiple companies.[4][5][6][7][8] The original memory modules were built upon ceramic substrates with 64K Hitachi "flip chip" parts and had pins, i.e. single in-line package (SIP) packaging.[1] SIMMs using pins are usually called SIP or SIPP memory modules to distinguish them from the more common modules using edge connectors.

The first variant of SIMMs has 30 pins and provides 8 bits of data (plus a 9th error-detection bit in parity SIMMs). They were used in AT-compatible (286-based, e.g., Wang APC[9]), 386-based, 486-based, Macintosh Plus, Macintosh II, Quadra, Atari STE microcomputers, Wang VS minicomputers and Roland electronic samplers.

The second variant of SIMMs has 72 pins and provides 32 bits of data (36 bits in parity and ECC versions). These appeared first in the early 1990s in later models of the IBM PS/2, and later in systems based on the 486, Pentium, Pentium Pro, early Pentium II, and contemporary/competing chips of other brands. By the mid-90s, 72-pin SIMMs had replaced 30-pin SIMMs in new-build computers, and were starting to themselves be replaced by DIMMs.

Non-IBM PC computers such as UNIX workstations may use proprietary non-standard SIMMs. The Macintosh IIfx uses proprietary non-standard SIMMs with 64 pins.

DRAM technologies used in SIMMs include FPM (Fast Page Mode memory, used in all 30-pin and early 72-pin modules), and the higher-performance EDO DRAM (used in later 72-pin modules).

Due to the differing data bus widths of the memory modules and some processors, sometimes several modules must be installed in identical pairs or in identical groups of four to fill a memory bank. The rule of thumb is a 286, 386SX, 68000 or low-end 68020 / 68030 (e.g. Atari Falcon, Mac LC) system (using a 16 bit wide data bus) would require two 30-pin SIMMs for a memory bank. On 386DX, 486, and full-spec 68020 through 68060 (e.g. Atari TT, Amiga 4000, Mac II) systems (32 bit data bus), either four 30-pin SIMMs or one 72-pin SIMM are required for one memory bank. On Pentium systems (data bus width of 64 bits), two 72-pin SIMMs are required. However, some Pentium systems have support for a "half bank mode", in which the data bus would be shortened to only 32 bits to allow operation of a single SIMM. Conversely, some 386 and 486 systems use what is known as "memory interleaving", which requires twice as many SIMMs and effectively doubles the bandwidth.

The earliest SIMM sockets were conventional push-type sockets. These were soon replaced by ZIF sockets in which the SIMM was inserted at an angle, then tilted into an upright position. To remove one, the two metal or plastic clips at each end must be pulled to the side, then the SIMM must be tilted back and pulled out (low-profile sockets reversed this convention somewhat, like SODIMMs - the modules are inserted at a "high" angle, then pushed down to become more flush with the motherboard). The earlier sockets used plastic retainer clips which were found to break, so steel clips replaced them.

Some SIMMs support presence detect (PD). Connections are made to some of the pins that encode the capacity and speed of the SIMM, so that compatible equipment can detect the properties of the SIMM. PD SIMMs can be used in equipment which does not support PD; the information is ignored. Standard SIMMs can easily be converted to support PD by fitting jumpers, if the SIMMs have solder pads to do so, or by soldering wires on.[10]

30-pin SIMMs

30-pin SIMM, 256 KB capacity
Two 30-pin SIMM slots on an IBM PS/2 model 50 motherboard

Standard sizes: 256 KB, 1 MB, 4 MB, 16 MB

30-pin SIMMS have 12 address lines, which can provide a total of 24 address bits. With an 8 bit data width, this leads to an absolute maximum capacity of 16 MB for both parity and non-parity modules (the additional redundancy bit chip usually does not contribute to the usable capacity).

30-pin SIMM Memory Module
Pin #NameSignal Description Pin #NameSignal Description
1VCC+5 VDC 16DQ4Data 4
2/CASColumn Address Strobe 17A8Address 8
3DQ0Data 0 18A9Address 9
4A0Address 0 19A10Address 10
5A1Address 1 20DQ5Data 5
6DQ1Data 1 21/WEWrite Enable
7A2Address 2 22VSSGround
8A3Address 3 23DQ6Data 6
9VSSGround 24A11Address 11
10DQ2Data 2 25DQ7Data 7
11A4Address 4 26QP*Data parity out
12A5Address 5 27/RASRow Address Strobe
13DQ3Data 3 28/CASP*Parity Column Address Strobe
14A6Address 6 29DP*Data parity in
15A7Address 7 30VCC+5 VDC

* Pins 26, 28 and 29 are not connected on non-parity SIMMs.

72-pin SIMMs

72-pin EDO DRAM SIMM

Standard sizes: 1 MB, 2 MB, 4 MB, 8 MB, 16 MB, 32 MB, 64 MB, 128 MB (the standard also defines 3.3 V modules with additional address lines and up to 2 GB)

With 12 address lines, which can provide a total of 24 address bits, two ranks of chips, and 32 bit data output, the absolute maximum capacity is 227 = 128 MB.

5 V 72-pin SIMM Memory Module
Pin #NameSignal Description Pin #NameSignal Description
1VSSGround 37MDP1*Data Parity 1 (MD8..15)
2MD0Data 0 38MDP3*Data Parity 3 (MD24..31)
3MD16Data 16 39VSSGround
4MD1Data 1 40/CAS0Column Address Strobe 0
5MD17Data 17 41/CAS2Column Address Strobe 2
6MD2Data 2 42/CAS3Column Address Strobe 3
7MD18Data 18 43/CAS1Column Address Strobe 1
8MD3Data 3 44/RAS0Row Address Strobe 0
9MD19Data 19 45/RAS1†Row Address Strobe 1
10VCC+5 VDC 46NCNot Connected
11NU [PD5#]Not Used [Presence Detect 5 (3v3)] 47/WERead/Write Enable
12MA0Address 0 48NC [/ECC#]Not Connected [ECC presence (if grounded) (3v3)]
13MA1Address 1 49MD8Data 8
14MA2Address 2 50MD24Data 24
15MA3Address 3 51MD9Data 9
16MA4Address 4 52MD25Data 25
17MA5Address 5 53MD10Data 10
18MA6Address 6 54MD26Data 26
19MA10Address 10 55MD11Data 11
20MD4Data 4 56MD27Data 27
21MD20Data 20 57MD12Data 12
22MD5Data 5 58MD28Data 28
23MD21Data 21 59VCC+5 VDC
24MD6Data 6 60MD29Data 29
25MD22Data 22 61MD13Data 13
26MD7Data 7 62MD30Data 30
27MD23Data 23 63MD14Data 14
28MA7Address 7 64MD31Data 31
29MA11Address 11 65MD15Data 15
30VCC+5 VDC 66NC [/EDO#]Not Connected [EDO presence (if grounded) (3v3)]
31MA8Address 8 67PD1xPresence Detect 1
32MA9Address 9 68PD2xPresence Detect 2
33/RAS3†Row Address Strobe 3 69PD3xPresence Detect 3
34/RAS2Row Address Strobe 2 70PD4xPresence Detect 4
35MDP2*Data Parity 2 (MD16..23) 71NC [PD (ref)#]Not Connected [Presence Detect (ref) (3v3)]
36MDP0*Data Parity 0 (MD0..7) 72VSSGround

* Pins 35, 36, 37 and 38 are not connected on non-parity SIMMs. [11]

†/RAS1 and /RAS3 are only used on two-rank SIMMS: 2, 8, 32, and 128 MB.

# These lines are only defined on 3.3V modules.

x Presence Detect signals are detailed in JEDEC Standard.

Proprietary SIMMs

GVP 64-pin

Several CPU cards from Great Valley Products for the Commodore Amiga used special 64-pin SIMMs (32 bits wide, 1, 4 or 16 MB, 60 ns).

Apple 64-pin

Dual-ported 64-pin SIMMs were used in Apple Macintosh IIfx computers to allow overlapping read/write cycles (1, 4, 8, 16 MB, 80 ns).[12][13]

5V 64-pin Mac IIfx SIMM Memory Module[14]
Pin #NameSignal Description Pin #NameSignal Description
1GNDGround 33Q4Data output bus, bit 4
2NCNot connected 34/W4Write-enable input for RAM IC 4
3+5V+5 volts 35A8Address bus, bit 8
4+5V+5 volts 36NCNot connected
5/CASColumn address strobe 37A9Address bus, bit 9
6D0Data input bus, bit 0 38A10Address bus, bit 10
7Q0Data output bus, bit 0 39A11Address bus, bit 11
8/W0Write-enable input for RAM IC 0 40D5Data input bus, bit 5
9A0Address bus, bit 0 41Q5Data output bus, bit 5
10NCNot connected 42/W5Write-enable input for RAM IC 5
11A1Address bus, bit 1 43NCNot connected
12D1Data input bus, bit 1 44NCNot connected
13Q1Data output bus, bit 1 45GNDGround
14/W1Write-enable input for RAM IC 1 46D6Data input bus, bit 6
15A2Address bus, bit 2 47Q6Data output bus, bit 6
16NCNot connected 48/W6Write-enable input for RAM IC 6
17A3Address bus, bit 3 49NCNot connected
18GNDGround 50D7Data input bus, bit 7
19GNDGround 51Q7Data output bus, bit 7
20D2Data input bus, bit 2 52/W7Write-enable input for RAM IC 7
21Q2Data output bus, bit 2 53/QBReserved (parity)
22/W2Write-enable input for RAM IC 2 54NCNot connected
23A4Address bus, bit 4 55/RASRow address strobe
24NCNot connected 56NCNot connected
25A5Address bus, bit 5 57NCNot connected
26D3Data input bus, bit 3 58QParity-check output
27Q3Data output bus, bit 3 59/WWPWrite wrong parity
28/W3Write-enable input for RAM IC 3 60PDCIParity daisy-chain input
29A6Address bus, bit 6 61+5V+5 volts
30NCNot connected 62+5V+5 volts
31A7Address bus, bit 7 63PDCOParity daisy-chain output
32D4Data input bus, bit 4 64GNDGround

HP LaserJet

72-pin SIMMs with non-standard Presence Detect (PD) connections.

See also

References

  1. 1 2 Clayton, James E. (1983). Low-cost, high-density memory packaging: A 64K X 9 DRAM SIP module, The International journal for hybrid microelectronics.
  2. ↑ U.S. Patent 4,656,605 - Single in-line memory module
  3. ↑ U.S. Patent 4,727,513 - Signal in-line memory module
  4. ↑ "Wang Laboratories, Inc., Plaintiff/cross-appellant, v. Toshiba Corporation; Toshiba America Electronic Components,inc.; Toshiba America Information Systems, Inc.,defendants-appellants,and Nec Corporation; Nec Electronics Inc. and Nec Technologies,inc., Defendants-appellants,and Molex Incorporated, Defendant, 993 F.2d 858 (Fed. Cir. 1993)". justia.com. May 10, 1993. Retrieved 22 December 2023.
  5. ↑ "Wang Laboratories, Inc., Plaintiff-appellee, v. Clearpoint Research Corporation, Defendant-appellant, 5 F.3d 1504 (Fed. Cir. 1993)". justia.com. July 23, 1993. Retrieved 22 December 2023.
  6. ↑ "Wang Laboratories v. MITSUBISHI ELECTRONICS, 860 F. Supp. 1448 (C.D. Cal. 1993)". justia.com. December 17, 1993. Retrieved 22 December 2023.
  7. ↑ "Wang Laboratories, Inc., Plaintiff-appellant, v. Mitsubishi Electronics America, Inc. and Mitsubishi Electric Corporation, Defendants/cross-appellants, 103 F.3d 1571 (Fed. Cir. 1997)". justia.com. January 3, 1997. Retrieved 22 December 2023.
  8. ↑ "Wang Laboratories v. OKI ELECTRIC INDUSTRY CO., 15 F. Supp. 2d 166 (D. Mass. 1998)". justia.com. July 31, 1998. Retrieved 22 December 2023.
  9. ↑ Wang Plays A Strong PC-Compatible Hand, PC Magazine, October 1, 1985
  10. ↑ Making Standard SIMMs Work – Memory Upgrade on the HP LaserJet 6MP/5MP Article on fitting jumpers to add Presence Detect to standard SIMMs
  11. ↑ JEDEC Standard No. 21-C, Section 4.4.2 "72 pin SIMM DRAM Module Family"
  12. ↑ Macintosh IIfx
  13. ↑ Apple Computer, Inc. (1990). Guide to the Macintosh Family Hardware (2nd ed.). Addison-Wesley, Inc. p. 230.
  14. ↑ Apple Computer, Inc. (1990). Guide to the Macintosh Family Hardware (2nd ed.). Addison-Wesley, Inc. pp. 214–222.
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