Epyc
General information
LaunchedJune 20, 2017 (2017-06-20)
Marketed byAMD
Designed byAMD
Common manufacturer(s)
Performance
Max. CPU clock rate2.7 GHz to 4.4 GHz
Architecture and classification
Technology node14 nm to 5 nm
Microarchitecture
Instruction setx86-64
Extensions
Physical specifications
Cores
  • up to 128 cores/256 threads per socket
Memory (RAM)
  • up to 12 memory channels at 4.8 GT/s
Socket(s)
Products, models, variants
Core name(s)
  • Naples
  • Rome
  • Milan
  • Genoa
  • Bergamo
  • Siena
Brand name(s)
  • Epyc
History
Predecessor(s)Opteron

Epyc is a brand of multi-core x86-64 microprocessors designed and sold by AMD, based on the company's Zen microarchitecture. Introduced in June 2017, they are specifically targeted for the server and embedded system markets.[1]

Epyc processors share the same microarchitecture as their regular desktop-grade counterparts, but have enterprise-grade features such as higher core counts, more PCI Express lanes, support for larger amounts of RAM, and larger cache memory. They also support multi-chip and dual-socket system configurations by using the Infinity Fabric interconnect.

History

In March 2017, AMD announced plans to re-enter the server market with a platform based on the Zen microarchitecture, codenamed Naples, and officially revealed it under the brand name Epyc in May.[2] That June AMD officially launched Epyc 7001 series processors, offering up to 32 cores per socket, and enabling performance that allowed Epyc to be competitive with the competing Intel Xeon product line.[3] Two years later, in August 2019, the Epyc 7002 "Rome" series processors, based on the Zen 2 microarchitecture, launched, doubling the core count per socket to 64, and increasing per-core performance dramatically over the last generation architecture.

In March 2021, AMD launched the Epyc 7003 "Milan" series, based on the Zen 3 microarchitecture.[4] Epyc Milan brought the same 64 cores as Epyc Rome, but with much higher per-core performance, with the Epyc 7763 beating the Epyc 7702 by up to 22 percent despite having the same number of cores and threads.[5] A refresh of the Epyc 7003 "Milan" series with 3D V-Cache, named Milan-X, launched on March 21, 2022, using the same cores as Epyc Milan, but with an additional 512 MB of cache stacked onto the compute dies, bringing the total amount of cache per CPU to 768 MB.[6]

In November 2021, AMD detailed the upcoming generations of Epyc, also unveiling the new LGA-6096 SP5 socket that would support the new generations of Epyc chips. Codenamed Genoa, the first Zen 4 based Epyc CPUs is built on TSMC's N5 node and supports up to 96 cores and 192 threads per socket, alongside 12 channels of DDR5,[7] 128 PCIe 5.0 lanes, and Compute Express Link 1.1.[8] AMD also shared information regarding the sister chip of Genoa, codenamed Bergamo. Bergamo will be based on a modified Zen 4 microarchitecture named Zen 4c, designed to allow for much higher core counts and efficiency at the cost of lower single-core performance, targeting cloud providers and workloads, compared to traditional high performance computing workloads.[9] Bergamo will be compatible with Socket SP5, and will support up to 128 cores and 256 threads per socket.[10]

In November 2022, AMD launched their 4th generation Epyc lineup, codenamed Genoa. Some tech reviewers and customers had already received hardware for testing and benchmarking, and third party benchmarks of Genoa parts were immediately available. The flagship part, the 96 core Epyc 9654, set records for multi-core performance, and showed up to 4× performance compared to Intel's flagship part, the Xeon 8380. High memory bandwidth and extensive PCIe connectivity removed many bottlenecks, allowing all 96 cores to be utilized in workloads where previous generation Milan chips would have been I/O-bound. Genoa was also the first x86 server CPU to support CXL, allowing for further expansion of memory and other devices with a high bandwidth interface built on PCIe 5.0.

In June 2023, AMD began shipping the 3D-Vcache enabled Genoa-X lineup, a refresh of Genoa that uses the same 3D die stacking technology as Milan-X to enable up to 1152 MB of L3 cache, a 50% increase over Milan-X, which had a maximum of 768 MB of L3 cache.[11] On the same day, AMD also announced the release of their cloud optimized Zen 4c SKUs, codenamed Bergamo, offering up to 128 cores per socket, utilizing a modified version of the Zen 4 core that was optimized for power efficiency and to reduce die space. Zen 4c cores do not have any instructions removed compared to standard Zen 4 cores, instead, the amount of cache per core is reduced from 4 MB to 2 MB, and the frequency of the cores is reduced.[12] Bergamo is socket compatible with Genoa, using the same SP5 socket and supporting the same CXL, PCIe, and DDR5 capacity as Genoa.[13]

In September 2023, AMD launched their low power and embedded 8004 series of CPUs, codenamed Siena. Siena utilizes a new socket, called SP6, which has a smaller footprint and pin count than the SP5 socket of its contemporary Genoa processors. Siena utilizes the same Zen 4c core architecture as Bergamo cloud native processors, allowing up to 64 cores per processor, and the same 6 nm I/O die as Bergamo and Genoa, although certain features have been cut down, such as reducing the memory support from 12 channels of DDR5 to only 6, and removing dual socket support.[14]

AMD Epyc CPU codenames follow the naming scheme of Italian cities, including Milan, Rome, Naples, Genoa, Bergamo and Siena.

AMD EPYC CPU codenames[15][16][17][18][19]
Segment Gen Year Name Product line Cores Socket
Server 1st 2017 Naples 7001 series 32× Zen SP3 (LGA)
2nd 2019 Rome 7002 series 64× Zen 2
3rd 2021 Milan 7003 series 64× Zen 3
2022 Milan-X
4th Genoa 9004 series 96× Zen 4 SP5 (LGA)
2023 Genoa-X
Bergamo 128× Zen 4c
Siena 8004 series 64× Zen 4c SP6 (LGA)
5th 2024 Turin TBA Zen 5 TBA
Embedded 1st 2018 Snowy Owl Embedded 3000 series 16× Zen SP4 (BGA)
2nd Naples Embedded 7001 series 32× Zen SP3 (BGA)
3rd Rome Embedded 7002 series 64× Zen 2
4th 2023 Genoa Embedded 9004 series 96× Zen 4 SP5 (BGA)

Design

A delidded second gen Epyc 7702, showing the die configuration

Epyc CPUs use a multi-chip module design to enable higher yields for a CPU than traditional monolithic dies. First generation Epyc CPUs are composed of four 14 nm compute dies, each with up to 8 cores.[20][21] Cores are symmetrically disabled on dies to create lower binned products with fewer cores but the same I/O and memory footprint. Second and Third gen Epyc CPUs are composed of eight compute dies built on a 7 nm process node, and a large input/output (I/O) die built on a 14 nm process node.[22] Third gen Milan-X CPUs use advanced through-silicon-vias to stack an additional die on top of each of the 8 compute dies, adding 64 MB of L3 cache per die.[23]

Epyc CPUs supports both single socket and dual socket operation. In a dual socket configuration, 64 PCIe lanes from each CPU are allocated to AMD's proprietary Infinity Fabric interconnect to allow for full bandwidth between both CPUs.[24] Thus, a dual socket configuration has the same number of usable PCIe lanes as a single socket configuration. First generation Epyc CPUs had 128 PCIe 3.0 lanes, while second and third generation had 128 PCIe 4.0 lanes. All current Epyc CPUs are equipped with up to eight channels of DDR4 at varying speeds, though next gen Genoa CPUs are confirmed by AMD to support up to twelve channels of DDR5.[7][25]

Unlike Opteron, Intel equivalents and AMD's desktop processors (excluding Socket AM1), Epyc processors are chipset-free - also known as system on a chip. That means most features required to make servers fully functional (such as memory, PCI Express, SATA controllers, etc.) are fully integrated into the processor, eliminating the need for a chipset to be placed on the mainboard. Some features may require the use of additional controller chips to utilize.

A near-infrared photograph of a delidded second gen Epyc 7702

Reception

Initial reception to Epyc was generally positive.[25] Epyc was generally found to outperform Intel CPUs in cases where the cores could work independently, such as in high-performance computing and big-data applications. First generation Epyc fell behind in database tasks compared to Intel's Xeon parts due to higher cache latency.[25] In 2021 Meta Platforms selected Epyc chips for its metaverse data centers.[26]

Epyc Genoa was well received, as it offered improved performance and efficiency compared to previous offerings, though received some criticism for not having 2 DIMMs per channel configurations validating, with some reviewers calling it an "incomplete platform".[27]

Products

Server

First generation Epyc (Naples)

The following table lists the devices using the first generation design.

A "P" suffix denotes support for only a single socket configuration. Non-P models use 64 PCIe lanes from each processor for the communication between processors.

Common features of EPYC 7001 series CPUs:

  • Socket: SP3.
  • All the CPUs support ECC DDR4-2666 in octa-channel mode (7251 supports only DDR4-2400).
  • L1 cache: 96 KB (32 KB data + 64 KB instruction) per core.
  • L2 cache: 512 KB per core.
  • All the CPUs support 128 PCIe 3.0 lanes.
  • Fabrication process: GlobalFoundries 14 nm.
Brand Model[lower-roman 1] Cores
(threads)		 Clock rate (GHz) L3 cache
(total)		 TDP Chiplets Core
config[lower-roman 2]		 Release
date		 Price
(1kU)		 Embedded
option[lower-roman 3]
Base Boost
All–core Max
EPYC 7251[28][29] 8 (16) 2.1 2.9 2.9 32 MB 120 W 4 × CCD 8 × 1 Jun 2017[30] US $475 Yes
7261[28][31] 2.5 64 MB 155/170 W Jun 2018[32] US $570 Yes
7281[28][29] 16 (32) 2.1 2.7 2.7 32 MB 8 × 2 Jun 2017[30] US $650 Yes
7301[28][29] 2.2 64 MB US $800 Yes
7351P[28][29] 2.4 2.9 2.9 US $750 735P
7351[28][29] US $1100 Yes
7371[28][33] 3.1 3.6 3.8 200 W Nov 2018[34] US $1550 Yes
7401P[28][29] 24 (48) 2.0 2.8 3.0 155/170 W 8 × 3 Jun 2017[30] US $1075 740P
7401[28][29] US $1850 Yes
7451[28][29] 2.3 2.9 3.2 180 W US $2400 Yes
7501[28][29] 32 (64) 2.0 2.6 3.0 155/170 W 8 × 4 US $3400 Yes
7551P[28][29] 2.55 180 W US $2100 755P
7551[28][29] US $3400 Yes
7571[35][36] 2.2 3.0 200 W Nov 2018 OEM/AWS Un­known
7601[28][29] 2.7 3.2 180 W Jun 2017[30] US $4200 Yes
  1. ↑ Models with "P" suffixes are uniprocessors, only available as single socket configuration.
  2. ↑ Core Complexes (CCX) × cores per CCX
  3. ↑ EPYC Embedded 7001 series models have identical specifications as EPYC 7001 series.
A first generation Epyc die configuration
An Epyc CPU in an SP3 socket

Second generation Epyc (Rome)

First generation Epyc processor

In November 2018, AMD announced Epyc 2 at their Next Horizon event, the second generation of Epyc processors codenamed "Rome" and based on the Zen 2 microarchitecture.[37] The processors feature up to eight 7 nm-based "chiplet" processors with a 14 nm-based IO chip providing 128 PCIe 4.0 lanes in the center interconnected via Infinity Fabric. The processors support up to 8 channels of DDR4 RAM up to 4 TB, and introduce support for PCIe 4.0. These processors have up to 64 cores with 128 SMT threads per socket.[38] The 7 nm "Rome" is manufactured by TSMC.[22] It was released on August 7, 2019.[39] It has 39.5 billion transistors.[40]

In April 2020, AMD launched three new SKUs using Epyc’s 7nm Rome platform. The three processors introduced were the eight-core Epyc 7F32, the 16-core 7F52 and the 24-core 7F72, featuring base clocks up to 3.7 GHz (up to 3.9 GHz with boost) within a TDP range of 180 to 240 watts. The launch was supported by Dell EMC, Hewlett Packard Enterprise, Lenovo, Supermicro, and Nutanix.[41]

Common features of these CPUs:

  • Codenamed "Rome"
  • Zen 2 Microarchitecture
  • 7 nm TSMC Process
  • SP3 Socket
  • The number of PCIe lanes: 128
  • Memory support: eight-channel DDR4-3200
Model Release
date		 Price
(USD)		 Fab Chiplets Cores
(threads)		 Core
config[lower-roman 1]		 Clock rate (GHz) Cache Socket
&
Scaling		 TDP
Base Boost L1 L2 L3
EPYC 7232P August 7,
2019		 $450 TSMC
7FF		 2 × CCD
1 × I/OD		 8 (16) 4 × 2 3.1 3.2 32 KB inst.
32 KB data
(per core)		 512 KB
(per core)		 32 MB
(8 MB per CCX)		 SP3
1P		 120 W
EPYC 7302P $825 4 × CCD
1 × I/OD		 16 (32) 8 × 2 3 3.3 128 MB
(16 MB per CCX)		 155 W
EPYC 7402P $1250 24 (48) 8 × 3 2.8 3.35 180 W
EPYC 7502P $2300 32 (64) 8 × 4 2.5 3.35
EPYC 7702P $4425 8 × CCD
1 × I/OD		 64 (128) 16 × 4 2 3.35 256 MB
(16 MB per CCX)		 200 W
EPYC 7252 $475 2 × CCD
1 × I/OD		 8 (16) 4 × 2 3.1 3.2 64 MB
(16 MB per CCX)		 SP3
(up to) 2P		 120 W
EPYC 7262 $575 4 × CCD
1 × I/OD		 8 × 1 3.2 3.4 128 MB
(16 MB per CCX)		 155 W
EPYC 7272 $625 2 × CCD
1 × I/OD		 12 (24) 4 × 3 2.9 3.2 64 MB
(16 MB per CCX)		 120 W
EPYC 7282 $650 16 (32) 4 × 4 2.8 3.2
EPYC 7302 $978 4 × CCD
1 × I/OD		 8 × 2 3 3.3 128 MB
(16 MB per CCX)		 155 W
EPYC 7352 $1350 24 (48) 8 × 3 2.3 3.2
EPYC 7402 $1783 8 × 3 2.8 3.35 180 W
EPYC 7452 $2025 32 (64) 8 × 4 2.35 3.35 155 W
EPYC 7502 $2600 8 × 4 2.5 3.35 180 W
EPYC 7532 $3350 8 × CCD
1 × I/OD		 16 × 2 2.4 3.3 256 MB
(16 MB per CCX)		 200 W
EPYC 7542 $3400 4 × CCD
1 × I/OD		 8 × 4 2.9 3.4 128 MB
(16 MB per CCX)		 225 W
EPYC 7552 $4025 6 × CCD
1 × I/OD		 48 (96) 12 × 4 2.2 3.3 192 MB
(16 MB per CCX)		 200 W
EPYC 7642 $4775 8 × CCD
1 × I/OD		 16 × 3 2.3 3.3 256 MB
(16 MB per CCX)		 225 W
EPYC 7662 $6150 64 (128) 16 × 4 2 3.3 225 W
EPYC 7702 $6450 2 3.35 200 W
EPYC 7742 $6950 2.25 3.4 225 W
EPYC 7H12 September 18, 2019 2.6 3.3 280 W
EPYC 7F32 April 14, 2020[42] $2100 4 × CCD
1 × I/OD		 8 (16) 8 × 1 3.7 3.9 128 MB
(16 MB per CCX)		 180 W
EPYC 7F52 $3100 8 × CCD
1 × I/OD		 16 (32) 16 × 1 3.5 3.9 256 MB
(16 MB per CCX)		 240 W
EPYC 7F72 $2450 6 × CCD
1 × I/OD		 24 (48) 12 × 2 3.2 3.7 192 MB
(16 MB per CCX)		 240 W
  1. ↑ Core Complexes (CCX) × cores per CCX
The bottom side of an Epyc CPU mounted in a plastic carrier

Third generation Epyc (Milan)

At the HPC-AI Advisory Council in the United Kingdom in October 2019, AMD stated specifications for Milan, Epyc chips based on the Zen 3 microarchitecture.[43] Milan chips will use Socket SP3, with up to 64 cores on package, and support eight-channel DDR4 RAM and 128 PCIe 4.0 lanes.[43] It also announced plans for the subsequent generation of chips, codenamed Genoa, that will be based on the Zen 4 microarchitecture and use Socket SP5.[43]

Milan CPUs were launched by AMD on March 15, 2021.[44]

Milan-X CPUs were launched March 21, 2022.[6] Milan-X CPUs use 3D V-Cache technology to increase the maximum L3 cache per socket capacity from 256 MB to 768 MB.[45][46][47]

Model Price
(USD)		 Fab Chiplets Cores
(threads)		 Core
config[lower-roman 1]		 Clock rate (GHz) Cache Socket
&
Scaling		 TDP
Base Boost L1 L2 L3
EPYC 7773X $8800 TSMC
7FF		 8 × CCD
1 × I/OD		 64 (128) 8 × 8 2.20 3.50 32 KB inst.
32 KB data
(per core)		 512 KB
(per core)		 768 MB
(96 MB per CCX)		 SP3
(up to) 2P		 280 W
EPYC 7763 $7890 2.45 3.40 256 MB
32 MB per CCX		 SP3
(up to) 2P		 280 W
EPYC 7713 $7060 2.00 3.675 225 W
EPYC 7713P $5010 SP3
1P
EPYC 7663 $6366 56 (112) 8 × 7 2.00 3.50 SP3
(up to) 2P		 240 W
EPYC 7663P $3139 SP3
1P
EPYC 7643 $4995 48 (96) 8 × 6 2.30 3.60 SP3
(up to) 2P		 225 W
EPYC 7643P $2722 SP3
1P
EPYC 7573X $5590 32 (64) 8 × 4 2.80 3.60 768 MB
(96 MB per CCX)		 SP3
(up to) 2P		 280 W
EPYC 75F3 $4860 2.95 4.00 256 MB
(32 MB per CCX)
EPYC 7543 $3761 2.80 3.70 225 W
EPYC 7543P $2730 256 MB
(32 MB per CCX)		 SP3
1P
EPYC 7513 $2840 2.60 3.65 128 MB
(16 MB per CCX)		 SP3
(up to) 2P		 200 W
EPYC 7453 $1570 4 × CCD
1 × I/OD		 28 (56) 4 × 7 2.75 3.45 64 MB
(16 MB per CCX)		 225 W
EPYC 7473X $3900 8 × CCD
1 × I/OD		 24 (48) 8 × 3 2.80 3.70 768 MB
(96 MB per CCX)		 240 W
EPYC 74F3 $2900 3.20 4.00 256 MB
(32 MB per CCX)
EPYC 7443 $2010 4 × CCD
1 × I/OD		 4 × 6 2.85 4.00 128 MB
(32 MB per CCX)		 200 W
EPYC 7443P $1337 SP3
1P
EPYC 7413 $1825 2.65 3.60 SP3
(up to) 2P		 180 W
EPYC 7373X $4185 8 × CCD
1 × I/OD		 16 (32) 8 × 2 3.05 3.80 768 MB
(96 MB per CCX)		 240 W
EPYC 73F3 $3521 3.50 4.00 256 MB
(32 MB per CCX)
EPYC 7343 $1565 4 × CCD
1 × I/OD		 4 × 4 3.20 3.90 128 MB
(32 MB per CCX)		 190 W
EPYC 7313 $1083 3.00 3.70 155 W
EPYC 7313P $913 SP3
1P
EPYC 7303 $604 2 × CCD
1 × I/OD		 2 x 8 2.40 3.40 64 MB
(32 MB per CCX)		 SP3
(up to) 2P		 130 W
EPYC 7303P $594 SP3
1P
EPYC 72F3 $2468 8 × CCD
1 × I/OD		 8 (16) 8 × 1 3.70 4.10 256 MB
(32 MB per CCX)		 SP3
(up to) 2P		 180 W
EPYC 7203 $348 2 × CCD
1 × I/OD		 2 x 4 2.80 3.40 64 MB
(32 MB per CCX)		 120 W
EPYC 7203P $338 SP3

1P

  1. ↑ Core Complexes (CCX) × cores per CCX

Fourth generation Epyc (Genoa, Bergamo and Siena)

On 10 November 2022, AMD launched the fourth generation of Epyc server and data center processors based on the Zen 4 microarchitecture, codenamed Genoa.[48] At their launch event, AMD announced that Microsoft and Google would be some of Genoa's customers.[49] Genoa features between 16 and 96 cores with support for PCIe 5.0 and DDR5. There was also an emphasis by AMD on Genoa's energy efficiency, which according to AMD CEO Lisa Su, means "lower total cost of ownership" for enterprise and cloud datacenter clients.[50] Genoa uses AMD's new SP5 (LGA-6096) socket.[51]
On June 13, 2023, AMD introduced Genoa-X with V-Cache technology for technical computing performance and Bergamo (9734, 9754 and 9754S) for cloud native computing.[52]
On September 18, 2023, AMD introduced the low power Siena lineup of processors, based on the Zen 4c microarchitecture. Siena supports up to 64 cores on the new SP6 socket, which is currently only used by Siena processors. Siena uses the same I/O die as Genoa, however certain features, such as dual socket support, are removed, and other features are reduced, such as the change from 12 channel memory support to 6 channel memory support.[53]

Model Release date Price
(USD)		 Fab Chiplets Cores
(Threads)		 Core
config[lower-roman 1]		 Clock rate
(GHz)		 Cache in MB Socket Socket
Count		 PCIe
lanes		 Memory
support		 TDP
Base Boost L1 L2 L3 DDR5 ECC
Low Power & Edge
8024P September 18, 2023 $409 TSMC
N5		 4 × CCD
1 × I/OD		 8 (16) 4 × 2 2.45 3.0 0.5 8 32 SP6 1P 96
PCIe 5.0		 DDR5-4800
six-channel		 Yes 90 W
8024PN $525 2.05 3.0 80 W
8124P $639 16 (32) 4 × 4 2.9 3.0 1 16 64 125 W
8124PN $790 2.0 3.0 100 W
8224P $855 24 (48) 4 × 6 2.55 3.0 1.5 24 160 W
8224PN $1,015 2.0 3.0 120 W
8324P $1,895 32 (64) 4 × 8 2.65 3.0 2 32 128 180 W
8324PN $2,125 2.05 3.0 130 W
8434P $2,700 48 (96) 4 × 12 2.5 3.1 3 48 200 W
8434PN $3,150 2.0 3.0 155 W
8534P $4,950 64 (128) 4 × 16 2.3 3.1 4 64 200 W
8534PN $5,450 2.0 3.1 155 W
Mainstream Enterprise
9124 November 10, 2022 $1,083 TSMC
N5		 4 × CCD
1 × I/OD		 16 (32) 4 × 4 3.0 3.7 1 16 64 SP5 1P/2P 128
PCIe 5.0		 DDR5-4800
twelve-channel		 Yes 200 W
9224 $1,825 24 (48) 4 × 6 2.5 3.7 1.5 24 200 W
9254 $2,299 4 × 6 2.9 4.15 128 220 W
9334 $2,990 32 (64) 4 × 8 2.7 3.9 2 32 210 W
9354 $3,420 8 × CCD
1 × I/OD		 8 × 4 3.25 3.75 256 280 W
9354P $2,730 1P
Performance Enterprise
9174F November 10, 2022 $3,850 TSMC
N5		 8 × CCD
1 × I/OD		 16 (32) 8 × 2 4.1 4.4 1 16 256 SP5 1P/2P 128
PCIe 5.0		 DDR5-4800
twelve-channel		 Yes 320 W
9184X June 13, 2023 $4,928 3.55 4.2 768
9274F November 10, 2022 $3,060 24 (48) 8 × 3 4.05 4.3 1.5 24 256
9374F $4,860 32 (64) 8 × 4 3.85 4.3 2 32
9384X June 13, 2023 $5,529 3.1 3.9 768
9474F November 10, 2022 $6,780 48 (96) 8 × 6 3.6 4.1 3 48 256 360 W
Cloud & High Performance Computing
9454 November 10, 2022 $5,225 TSMC
N5		 8 × CCD
1 × I/OD		 48 (96) 8 × 6 2.75 3.8 3 48 256 SP5 1P/2P 128
PCIe 5.0		 DDR5-4800
twelve-channel		 Yes 290 W
9454P $4,598 1P
9534 $8,803 64 (128) 8 × 8 2.45 3.7 4 64 1P/2P 280 W
9554 $9,087 3.1 3.75 360 W
9554P $7,104 1P
9634 $10,304 12 × CCD
1 × I/OD		 84 (168) 12 × 7 2.25 3.7 5.25 84 384 1P/2P 290 W
9654 $11,805 96 (192) 12 × 8 2.4 3.7 6 96 360 W
9654P $10,625 1P
9684X June 13, 2023 $14,756 2.55 3.7 1152 1P/2P 400 W
9734 $9,600 8 × CCD
1 × I/OD		 112 (224) 8 x 14 2.2 3.0 7 112 256 340 W
9754S $10,200 128 (128) 8 x 16 2.25 3.1 8 128 360 W
9754 $11,900 128 (256)
  1. ↑ Core Complexes (CCX) × cores per CCX

Embedded

First generation Epyc (Snowy Owl)

In February 2018, AMD also announced the Epyc 3000 series of embedded Zen CPUs.[54]

Common features of EPYC Embedded 3000 series CPUs:

  • Socket: SP4 (31xx and 32xx models use SP4r2 package).
  • All the CPUs support ECC DDR4-2666 in dual-channel mode (3201 supports only DDR4-2133), while 33xx and 34xx models support quad-channel mode.
  • L1 cache: 96 KB (32 KB data + 64 KB instruction) per core.
  • L2 cache: 512 KB per core.
  • All the CPUs support 32 PCIe 3.0 lanes per CCD (max 64 lanes).
  • Fabrication process: GlobalFoundries 14 nm.
Brand Model Cores
(threads)		 Clock rate (GHz) L3 cache
(total)		 TDP Chiplets Core
config[lower-roman 1]		 Release
date
Base Boost
All-core Max
EPYC
Embedded		 3101[55] 4 (4) 2.1 2.9 2.9 8 MB 35 W 1 x CCD 1 × 4 Feb 2018
3151[55] 4 (8) 2.7 16 MB 45 W 2 × 2
3201[55] 8 (8) 1.5 3.1 3.1 30 W 2 × 4
3251[55] 8 (16) 2.5 55 W
3255[56] 25–55 W Dec 2018
3301[55] 12 (12) 2.0 2.15 3.0 32 MB 65 W 2 x CCD 4 × 3 Feb 2018
3351[55] 12 (24) 1.9 2.75 60–80 W
3401[55] 16 (16) 1.85 2.25 85 W 4 × 4
3451[55] 16 (32) 2.15 2.45 80–100 W
  1. ↑ Core Complexes (CCX) × cores per CCX

Chinese variants

A variant created for the Chinese server market by an AMD–Chinese joint venture is the Hygon Dhyana system on a chip.[57][58] It is noted to be a variant of the AMD Epyc, and is so similar that "there is little to no differentiation between the chips".[57] It has been noted that there is "less than 200 lines of new kernel code" for Linux kernel support, and that the Dhyana is "mostly a re-branded Zen CPU for the Chinese server market".[58] Later Benchmarks showed that certain floating point instructions are performing worse, probably to comply with US export restrictions.[59] AES and other western cryptography algorithms are replaced by Chinese variants throughout the design.[59]

References

  1. ↑ Cutress, Ian (30 May 2017). "Computex 2017: AMD Press Event Live Blog". AnandTech. Retrieved November 7, 2022.
  2. ↑ Kampman, Jeff (May 16, 2017). "AMD's Naples datacenter CPUs will make an Epyc splash". Tech Report. Retrieved May 16, 2017.
  3. ↑ Cutress, Ian (June 20, 2017). "AMD's Future in Servers: New 7000-Series CPUs Launched and EPYC Analysis". AnandTech. Retrieved July 12, 2017.
  4. ↑ Alcorn, Paul (March 15, 2021). "Watch AMD's Epyc 7003 Milan Launch Here". Tom's Hardware. Retrieved April 5, 2022.
  5. ↑ "AMD EPYC 7763 vs AMD EPYC 7702 [cpubenchmark.net] by PassMark Software". CPU Benchmark. Retrieved April 5, 2022.
  6. 1 2 "AMD EPYC 7003 "Milan-X" launches March 21st, specs and pricing leaked". VideoCardz. March 20, 2022. Retrieved March 25, 2022.
  7. 1 2 Cutress, Ian (November 8, 2021). "AMD Gives Details on EPYC Zen4: Genoa and Bergamo, up to 96 and 128 Cores". AnandTech. Retrieved April 5, 2022.
  8. ↑ Mujtaba, Hassan (February 28, 2021). "AMD EPYC Genoa CPU Platform Detailed - Up To 96 Zen 4 Cores, 192 Threads, 12-Channel DDR5-5200, 128 PCIe Gen 5 Lanes, SP5 'LGA 6096' Socket". Wccftech. Retrieved April 5, 2022.
  9. ↑ servethehome (November 8, 2021). "AMD Bergamo to hit 128 Cores and Genoa at 96 Cores". ServeTheHome. Retrieved April 5, 2022.
  10. ↑ Mujtaba, Hassan (January 10, 2022). "Another AMD EPYC Genoa 'Zen 4' CPU Leaks Out, This Time A 16 Core Chip With 2 Active CCDs". Wccftech. Retrieved April 5, 2022.
  11. ↑ Smith, Ryan. "AMD: EPYC "Genoa-X" CPUs With 1.1GB of L3 Cache Now Available". www.anandtech.com. Retrieved 2023-09-26.
  12. ↑ Kennedy, Patrick (2023-07-19). "AMD EPYC Bergamo is a Fantastically Fresh Take on Cloud Native Compute". ServeTheHome. Retrieved 2023-09-27.
  13. ↑ Kennedy, Patrick (2023-07-19). "AMD EPYC Bergamo is a Fantastically Fresh Take on Cloud Native Compute". ServeTheHome. Retrieved 2023-09-26.
  14. ↑ Kennedy, Patrick (2023-09-18). "AMD EPYC 8004 Siena Launched for Lower Power EPYC Edge". ServeTheHome. Retrieved 2023-09-26.
  15. ↑ Cutress, Ian (May 27, 2019). "AMD Confirms Zen 4 EPYC Codename, and Elaborates on Frontier Supercomputer CPU". AnandTech. Retrieved November 7, 2022.
  16. ↑ Bonshor, Gavin (June 9, 2022). "AMD Updated EPYC Roadmap: 5th Gen EPYC "Turin" Announced, Coming by End of 2024". AnandTech. Retrieved November 7, 2022.
  17. ↑ btarunr (June 10, 2022). "AMD Announces the "Zen 5" Microarchitecture and EPYC "Turin" Processor on 4nm". TechPowerUp. Retrieved November 15, 2022.
  18. ↑ Shilov, Anthon (March 14, 2023). "AMD Rolls Out EPYC Embedded 9004 CPUs: Up to 96 Cores". Tom's Hardware. Retrieved June 15, 2023.
  19. ↑ Shilov, Anthon (September 18, 2023). "AMD Launches EPYC 8004-Series 'Siena' CPUs: Up to 64 Zen 4c Cores". Tom's Hardware. Retrieved September 18, 2023.
  20. ↑ Cutress, Ian (March 7, 2017). "AMD Prepares 32-Core Naples CPUs for 1P and 2P Servers: Coming in Q2". AnandTech. Retrieved March 7, 2017.
  21. ↑ Morris, John (March 13, 2018). "Inside GlobalFoundries' long road to the leading edge". ZDNet. Retrieved July 17, 2019.
  22. 1 2 Smith, Ryan (July 26, 2018). "AMD "Rome" EPYC CPUs to Be Fabbed By TSMC". AnandTech. Retrieved June 18, 2019.
  23. ↑ Trader, Tiffany (March 21, 2022). "AMD Milan-X CPU with 3D V-Cache Available in Four SKUs, Up to 64-Cores". HPC Wire. Retrieved May 6, 2022.
  24. ↑ Johnson, Renee (March 7, 2017). "AMD's Naples platform prepares to take Zen into the datacenter". Tech Report. Retrieved March 7, 2017.
  25. 1 2 3 De Gelas, Johan; Cutress, Ian (July 11, 2017). "Sizing Up the Servers: Intel's Skylake-SP Xeon vs AMD's EPYC 7000". AnandTech. Retrieved July 11, 2017.
  26. ↑ Sozzi, Brian (November 8, 2021). "Chipmaker AMD just scored a big deal with Meta". Yahoo! Finance. Retrieved November 10, 2022.
  27. ↑ Kennedy, Patrick (November 22, 2022). "Gigabyte has a 48 DIMM 2P AMD EPYC Genoa GPU Server at SC22". ServeTheHome. Retrieved November 26, 2022.
  28. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 "AMD EPYC 7000 Series Processors" (PDF). AMD. January 2019. Retrieved March 25, 2023.
  29. 1 2 3 4 5 6 7 8 9 10 11 12 Cutress, Ian (June 20, 2017). "AMD's Future in Servers: New 7000-Series CPUs Launched and EPYC Analysis". AnandTech. Retrieved June 21, 2017.
  30. 1 2 3 4 Kennedy, Patrick (May 16, 2017). "AMD EPYC New Details on the Emerging Server Platform". ServeTheHome. Retrieved May 16, 2017.
  31. ↑ "AMD EPYC 7261 - PS7261BEV8RAF". CPU-World. March 26, 2023.
  32. ↑ Kennedy, Patrick (October 31, 2018). "AMD EPYC 7261 8 Core CPU Quietly Launched L3 Cache Monster". ServeTheHome. Retrieved March 28, 2023.
  33. ↑ "AMD EPYC 7371 - PS7371BDVGPAF". CPU-World. March 26, 2023.
  34. ↑ "New AMD-Powered Supercomputers Unleash Discovery and Accelerate Innovation" (Press release). AMD. November 13, 2018. Retrieved March 28, 2023.
  35. ↑ "AMD EPYC 7571 - PS7571BDVIHAF". CPU-World. March 25, 2023.
  36. ↑ Larabel, Michael (November 7, 2018). "A Look At The AMD EPYC Performance On The Amazon EC2 Cloud". Phoronix. Retrieved March 28, 2023.
  37. ↑ "AMD Takes High-Performance Datacenter Computing to the Next Horizon". AMD (Press release). San Francisco, CA. November 6, 2018. Retrieved December 6, 2018.
  38. ↑ Ung, Gordon (November 7, 2018). "What AMD's 64-core 'Rome' server CPU tells us about Ryzen 2". PCWorld. Retrieved November 11, 2018.
  39. ↑ "2nd Gen AMD EPYC Processors Set New Standard for the Modern Datacenter with Record-Breaking Performance and Significant TCO Savings". AMD (Press release). Santa Clara, CA. August 7, 2019. Retrieved August 8, 2019.
  40. ↑ S. Smith, Matthew (2022). "Single-Chip Processors Have Reached Their Limits". IEEE Spectrum. 59 (7): 11.
  41. ↑ Trader, Tiffany (April 14, 2020). "AMD Launches Three New High-Frequency Epyc SKUs Aimed at Commercial HPC". www.hpcwire.com.
  42. ↑ "New 2nd Gen AMD EPYC™ Processors Redefine Performance for Database, Commercial HPC and Hyperconverged Workloads". AMD. April 14, 2020.
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  44. ↑ Trader, Tiffany (March 15, 2021). "AMD Launches Epyc 'Milan' with 19 SKUs for HPC, Enterprise and Hyperscale". HPC Wire. Retrieved November 10, 2022.
  45. ↑ Sandhu, Tarinder (March 21, 2022). "A deeper look into AMD Epyc 7003 Milan-X featuring 3D V-Cache". Club386. Retrieved November 10, 2022.
  46. ↑ Bonshor, Gavin (March 21, 2022). "AMD Releases Milan-X CPUs With 3D V-Cache: EPYC 7003 Up to 64 Cores and 768 MB L3 Cache". AnandTech. Retrieved November 10, 2022.
  47. ↑ "AMDs Exascale-Hammer: Epyc 3 mit 804 MByte Cache, Instinct MI200 mit 47,9 TFlops". c't Magazin (in German). November 8, 2021. Retrieved November 10, 2022.
  48. ↑ Mujtaba, Hassan (10 November 2022). "AMD 4th Gen EPYC 9004 "Genoa Zen 4" CPUs Launched: Up To 96 Cores, 192 Threads, 384 MB L3 Cache & Crushing All Other Server Chips". Wccftech. Retrieved November 11, 2022.
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  50. ↑ Burt, Jeffrey (November 10, 2022). "The Acute Role Reversal for AMD and Intel in Datacenter Compute". The Next Platform. Retrieved November 11, 2022.
  51. ↑ Alcorn, Paul (November 10, 2022). "AMD 4th-Gen EPYC Genoa 9654, 9554, and 9374F Review: 96 Cores, Zen 4 and 5nm Disrupt the Data Center". Tom's Hardware. Retrieved November 11, 2022.
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  56. ↑ "AMD EPYC Embedded 3255 - PE3255BGR88AF". CPU-World. March 26, 2023.
  57. 1 2 Alcorn, Paul (July 6, 2018). "China Finds Zen: Begins Production Of x86 Processors Based On AMD's IP". Tom's Hardware. Retrieved July 9, 2018.
  58. 1 2 Larabel, Michael (June 9, 2018). "Hygon Dhyana: Chinese x86 Server CPUs Based On AMD Zen". Phoronix. Retrieved July 9, 2018.
  59. 1 2 Cutress, Ian; Wilson, Wendell (February 27, 2020). "Testing a Chinese x86 CPU: A Deep Dive into Zen-based Hygon Dhyana Processors". AnandTech. Retrieved September 29, 2020.
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