A frequency divider, also called a clock divider or scaler or prescaler, is a circuit that takes an input signal of a frequency, ${\displaystyle f_{in}}$, and generates an output signal of a frequency:

${\displaystyle f_{out}={\frac {f_{in}}{N}}}$

where ${\displaystyle N}$ is an integer. Phase-locked loop frequency synthesizers make use of frequency dividers to generate a frequency that is a multiple of a reference frequency. Frequency dividers can be implemented for both analog and digital applications.

Analog

Analog frequency dividers are less common and used only at very high frequencies. Digital dividers implemented in modern IC technologies can work up to tens of GHz.

Regenerative

A regenerative frequency divider, also known as a Miller frequency divider,^[1] mixes the input signal with the feedback signal from the mixer.

Regenerative frequency divider

The feedback signal is ${\displaystyle f_{in}/2}$. This produces sum and difference frequencies ${\displaystyle f_{in}/2}$, ${\displaystyle 3f_{in}/2}$ at the output of the mixer. A low pass filter removes the higher frequency, and the ${\displaystyle f_{in}/2}$ frequency is amplified and fed back into the mixer.

Digital

An animation of a frequency divider implemented with D flip-flops, counting from 0 to 7 in binary

For power-of-2 integer division, a simple binary counter can be used, clocked by the input signal. The least-significant output bit alternates at 1/2 the rate of the input clock, the next bit at 1/4 the rate, the third bit at 1/8 the rate, etc. An arrangement of flipflops is a classic method for integer-n division. Such division is frequency and phase coherent to the source over environmental variations, including temperature. The easiest configuration is a series where each flip-flop is a divide-by-2. For a series of three of these, such a system would be a divide-by-8. By adding additional logic gates to the chain of flip-flops, other division ratios can be obtained. Integrated circuit logic families can provide a single-chip solution for some common division ratios.

Another popular circuit to divide a digital signal by an even integer multiple is a Johnson counter. This is a type of shift register network that is clocked by the input signal. The last register's complemented output is fed back to the first register's input. The output signal is derived from one or more of the register outputs. For example, a divide-by-6 divider can be constructed with a 3-register Johnson counter. The six valid values of the counter are 000, 100, 110, 111, 011, and 001. This pattern repeats each time the input signal clocks the network. The output of each register is an f/6 square wave with 120° of phase shift between registers. Additional registers can be added to provide additional integer divisors.

Fractional-N synthesis

A fractional-n frequency synthesizer can be constructed using two integer dividers, a divide-by-N, and a divide-by-(N + 1) frequency divider. With a modulus controller, N is toggled between the two values so that the VCO alternates between one locked frequency and the other. The VCO stabilizes at a frequency that is the time average of the two locked frequencies. By varying the percentage of time the frequency divider spends at the two divider values, the frequency of the locked VCO can be selected with very fine granularity.

See also

• Pulse-swallowing counter

References

External links

Wikimedia Commons has media related to Frequency dividers.

• Delta-sigma fractional-n synthesizers
• A Study of High Frequency Regenerative Frequency Dividers

Digital frequency dividers

• Divide by 2, and asynchronous 2^N Ripple Counter dividers - Electronics Tutorials
• Synchronous divide by 3, 6, 9, 12 with 50% duty cycle output - ON Semiconductor
• Synchronous divide by 3 or 5 with 50% duty cycle output, and divide by 1.5 & 2.5 circuits - Xilinx
• Divide by N-0.5 using 74x161 counters - Whitepaper